Circuit architecture for an integrated circuit
View Patent ↗An integrated circuit comprising at least one group comprising having multiple arithmetic/logic units arranged in sub-groups. In the sub-groups at inputs of multiple arithmetic/logic units, in each case a single one of the first selection units is connected on the input side, wherein no other selection unit is connected directly on the input side of this selection unit. The first selection units are coupled to each other such that a horizontal and/or vertical logical interconnection of the arithmetic/logic units within a group, and/or a logical interconnection of arithmetic/logic units to an upstream group can be implemented. Second selection units are in each case connected on the output side of a column of arithmetic/logic units. The second selection units of a group are connected on the output side to one bus each, and a microprocessor is coupled to this bus.
1. An integrated circuit, comprising:
a plurality of circuit groups each comprising a plurality of circuit sub-groups, where each circuit sub-group comprises
a first selection unit that receives a first signal from an upstream arithmetic logic unit in addition to a second signal, and provides a first selected signal to a downstream arithmetic logic unit that provides a third signal to a second selection unit that also receives a fourth signal, where the second selection unit provides a second selected signal to a second downstream arithmetic logic unit, which provides a fifth signal to a buffer that provides a sixth signal;
a processor; and
a bus that receives the plurality of sixth signals from the plurality of circuit sub-groups and selectively routes a selected one of the sixth signals to the processor that is also connected to the bus,
where the first and second selection units are dynamically configured during run-time of an executable routine within the processor.
2. The integrated circuit of claim 1 , where the processor comprises one of a CPU, a digital signal processor, or a state machine.
3. The integrated circuit of claim 1 , where the first selection units comprise multiplexers.
4. The integrated circuit of claim 1 , where the first selection units are controllable by mask programming.
5. The integrated circuit of claim 1 , where the first selection units are controllable through decoders and memories.
6. The integrated circuit of claim 1 , where the first selection units are controllable through registers.
7. The integrated circuit of claim 1 , where the buffers comprise tristate buffers.
8. The integrated circuit of claim 1 , where at least some of the arithmetic logic units comprise multiply/accumulate units.
9. The integrated circuit of claim 1 , where at least some of the arithmetic logic units comprise dividers.
10. The integrated circuit of claim 1 ,
where at least one of the upstream arithmetic logic unit and the downstream arithmetic logic unit is configured as at least one of a multiply/accumulate unit and a divider.
11. An integrated circuit, comprising:
a processor;
a plurality of circuit groups, each circuit group comprising a plurality of circuit sub-groups and a bus, each circuit sub-group comprising
n circuit pairs, each circuit pair including a first selection unit and an arithmetic logic unit, which first selection unit provides a first output signal, and which arithmetic logic unit receives the first output signal and provides a second output signal, where the first selection unit in a first one of the circuit pairs receives at least one input signal, and where the first selection unit in a n th one of the circuit pairs receives the second output signal from the arithmetic logic unit in a (n-1) th one of the circuit pairs within a respective circuit sub-group and the second output signal from the arithmetic logic unit in the (n-1) th one of the circuit pairs within another one of the circuit sub-groups, and provides a second output signal; and
a second selection unit that receives the second output signal from the arithmetic logic unit in the n th one of the circuit pairs and provides a third output signal;
where the bus receives the third output signal from the second selection unit in each of the circuit sub-groups and selectively routes a selected one of the third output signals to the processor; and
where the bus in at least one of the circuit groups provides a fourth output signal to a third selection unit in communication with the bus in another one of the circuit groups.