Strained semiconductor device and method of making same
View Patent ↗In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress.
1. A method of making a semiconductor device, the method comprising:
providing a semiconductor body;
forming a gate dielectric over the semiconductor body;
forming a floating gate over the gate dielectric;
forming an insulating region over the floating gate;
forming a control gate over the insulating region;
forming a first spacer at sidewalls of the floating gate and control gate;
forming a second spacer adjacent the first spacer;
implanting dopants into the semiconductor body adjacent the second spacer;
removing the second spacer; and
forming a stress inducing liner over the semiconductor body.
2. The method according to claim 1 , wherein forming a control gate comprises simultaneously forming a gate for a logic transistor.
3. The method of claim 2 , wherein the logic transistor comprises a p-channel transistor and wherein forming a stress inducing liner comprises forming a compressively stressed liner over the logic transistor and over the control gate.
4. A method of forming a semiconductor device, the method comprising:
forming a gate stack over a semiconductor body, the gate stack comprising a gate dielectric region over the semiconductor body, a floating gate over the gate dielectric region, a control gate over the floating gate and an inter-gate dielectric between the floating gate and the control gate, wherein the gate dielectric region comprises a stressed gate dielectric region having an energy gap that is greater than a band gap of a relaxed gate dielectric region of the same material;
forming a doped extension region within the semiconductor body and extending from a point adjacent the gate outward a first distance from the gate;
forming a source/drain region within the semiconductor body and extending from a point at the first distance from the gate; and
forming a spacer at a sidewall of the gate, the spacer overlying only a portion of the doped extension region, the spacer having a thickness less than the first distance.
5. The method of claim 4 , further comprising forming a logic transistor disposed at a surface of the semiconductor body spaced from the gate stack.
6. The method of claim 5 , wherein forming a logic transistor comprises forming a logic transistor with a compressively strained channel.
7. The method of claim 5 , wherein forming a logic transistor comprises forming a logic transistor with a tensilely strained channel.
8. The method of claim 1 , wherein the stress inducing liner changes a band gap of the gate dielectric.