Integrated CMOS-MEMS technology for wired implantable sensors

1 . Apparatus comprising:

a first substrate comprising a ceramic material;

an integrated circuit formed on the first substrate;

at least one conductive feedthrough formed through the first substrate that is in electrical communication with the integrated circuit; and

a second substrate comprising a ceramic material that is hermetically sealed to the first substrate to define an cavity that encloses the integrated circuit, which cavity and integrated circuit cooperate to provide a sensing apparatus.

2 . The apparatus recited in claim 1 further comprising:

a pair of lower capacitor electrodes formed on the first substrate that are respectively coupled to the integrated circuit;

wherein the second substrate is configured to have a deflective region that changes position in response to pressure; and

an upper capacitor electrode formed on the deflective region.

3 . The apparatus recited in claim 1 wherein the first and second substrates are comprised of glass, fused silica, sapphire, quartz or silicon.

4 . The apparatus recited in claim 3 wherein the integrated circuit is passivated using silicon nitride.

5 . Apparatus comprising:

a first fused silica substrate;

an integrated circuit formed on the first fused silica substrate;

a feedthrough formed through the first fused silica substrate that in electrical communication with the integrated circuit; and

a second fused silica substrate sealed to the first fused silica substrate to define a cavity that encloses the integrated circuit, which cavity and integrated circuit cooperate to provide a sensing apparatus.

6 . The apparatus recited in claim 5 further comprising:

at least one lower capacitor electrode formed on the first fused silica substrate;

a deflective region that changes position in response to pressure formed in the cavity; and

an upper capacitor electrode formed on the deflective region.

7 . A method of fabricating implantable pressure sensing apparatus comprising:

providing a first substrate comprising a ceramic material;

forming a polysilicon layer on the first substrate;

fabricating an integrated circuit adjacent to a surface of the first substrate;

forming a passivation layer on the integrated circuit;

forming a conductive area on the passivation layer that provides electrical communication to the integrated circuit;

forming a feedthrough through the first substrate that contacts the conductive area that provides for external electrical communication to the integrated circuit; and

fusing a second substrate comprising a ceramic material to the first substrate to form a hermetic cavity that encases the integrated circuit.

8 . The method recited in claim 7 wherein the first and second substrates comprise fused silica.

9 . The method recited in claim 7 further comprising annealing the polysilicon layer to provide stress relief.

10 . The method recited in claim 7 wherein the integrated circuit fabricated by:

forming an active area in the polysilicon layer;

forming source and drain electrodes in the active area;

growing gate oxide on the substrate; and

forming a gate on the gate oxide.

11 . The method recited in claim 7 wherein the active area in the polysilicon layer and the source and drain electrodes are formed using photolithography and ion implantation.

12 . The method recited in claim 7 wherein the gate comprises metal or polysilicon.

13 . The method recited in claim 7 where the integrated circuit is passivated using silicon nitride.