Apparatus for and method of controlling a digital demodulator coupled to an equalizer
View Patent ↗A method of controlling a digital demodulator ( 922 ) coupled to an equalizer ( 930 ) includes the steps of generating an equalizer value ( 930 A), filtering ( 944 ) the equalizer value ( 930 A) to obtain a post filter output, subtracting the equalizer output signal ( 930 C) from the decoded data ( 930 D) and generating an error value ( 924 A). The post filter output is correlated ( 948 ) with the error value ( 924 A) to obtain a correlated value ( 74 A). A control signal is developed from the correlated value and is used to adjust the digital demodulator ( 922 ).
1. A method of controlling a digital demodulator coupled to an equalizer, the method comprising the steps of:
generating an equalizer value;
filtering the equalizer value to obtain a post filter output;
subtracting an equalizer output signal from decoded data and generating an error value;
correlating the post filter output with the error value to obtain a correlated value;
developing a control signal from the correlated value; and
adjusting the digital demodulator using the control signal.
2. The method of claim 1 , wherein the digital demodulator comprises a digital mixer and wherein the digital mixer precedes the equalizer.
3. The method of claim 1 , wherein the equalizer is adapted to receive ATSC compliant signals.
4. The method of claim 1 , wherein the equalizer is adapted to receive ADTB-T compliant signals.
5. The method of claim 1 , wherein the equalizer value comprises an output of a feedforward filter of the equalizer.
6. The method of claim 1 , wherein the equalizer value comprises an input to a decision device of the equalizer.
7. The method of claim 6 , wherein the decision device comprises a decision slicer.
8. The method of claim 6 , wherein the decision device comprises a trellis decoder.
9. The method of claim 8 , wherein the trellis decoder utilizes a Viterbi algorithm.
10. The method of claim 1 , wherein the post filter output comprises an in-phase signal and a quadrature signal.
11. The method of claim 1 , wherein the correlating step includes the step of temporally aligning the post filter output and the error value.
12. The method of claim 1 , wherein the filtering step is undertaken by a phase-shift filter.
13. The method of claim 12 , wherein the phase-shift filter is a quadrature filter.
14. The method of claim 12 , wherein the phase-shift filter is a Hilbert filter.
15. The method of claim 1 , wherein the correlating step is undertaken by a multiplier.
16. The method of claim 1 , wherein the developing step is undertaken by a loop filter.
17. The method of claim 1 , wherein the adjusting step is undertaken by a digital mixer.
18. The method of claim 1 , wherein the adjusting step includes the step of adjusting an oscillator.
19. The method of claim 18 , wherein the oscillator is a numerically controlled oscillator.
20. A post filter for controlling a digital demodulator coupled to an equalizer, comprising:
means for generating an equalizer value;
means for filtering the equalizer value to obtain a post filter output;
means for subtracting an equalizer output signal from decoded data and generating an error value;
means for correlating the post filter output with the error value to obtain a correlated value;
means for developing a control signal from the correlated value; and
means for adjusting the digital demodulator using the control signal.
21. The post filter of claim 20 , wherein the equalizer value comprises an input to a decision device of the equalizer.
22. The post filter of claim 21 , wherein the decision device comprises a decision slicer.
23. The post filter of claim 21 , wherein the decision device comprises a trellis decoder.
24. The post filter of claim 23 , wherein the trellis decoder utilizes a Viterbi algorithm.
25. A computer-readable medium for controlling a digital demodulator coupled to an equalizer, including programming for implementing:
a first routine for generating an equalizer value;
a second routine for filtering the equalizer value to obtain a post filter output;
a third routine for subtracting an equalizer output signal from decoded data and generating an error value;
a fourth routine for correlating the post filter output with the error value to obtain a correlated value;
a fifth routine for developing a control signal from the correlated value; and
a sixth routine for adjusting the digital demodulator using the control signal.
26. The computer-readable medium of claim 25 , wherein the equalizer value comprises an input to a decision device of the equalizer.
27. The computer-readable medium of claim 26 , wherein the decision device comprises a decision slicer.
28. The computer-readable medium of claim 26 , wherein the decision device comprises a trellis decoder.
29. The computer-readable medium of claim 28 , wherein the trellis decoder utilizes a Viterbi algorithm.