Semiconductor integrated circuit
View Patent ↗An apparatus is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.
1. A semiconductor integrated circuit comprising:
a memory cell including a storage transistor for storing an electric charge in a gate capacitance;
a write bit line coupled to a gate electrode of the storage transistor;
a read bit line coupled to a drain electrode of the storage transistor; and
a switching element provided between a source electrode of the storage transistor and a power supply;
wherein the switching element controls a potential of the source electrode of the storage transistor so that in a standby state the source electrode stays in a floating state, and in a read operation state the potential of the source electrode becomes a power supply potential.
2. A semiconductor integrated circuit according to claim 1 , further comprising:
an access transistor for controlling conduction between the read bit line and the drain electrode of the storage transistor.
3. A semiconductor integrated circuit according to claim 1 , further comprising:
a write transistor for supplying the electric charge from the write bit line to the gate electrode of the storage transistor.
4. A semiconductor integrated circuit according to claim 3 ,
wherein a channel area of the write transistor is formed of a film having a film thickness of 5 nm or less.
5. A semiconductor integrated circuit according to claim 4 ,
wherein a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
6. A semiconductor integrated circuit according to claim 1 , further comprising:
a second memory cell provided with the switching element in common.
7. A semiconductor integrated circuit comprising:
a memory cell including a storage transistor for storing an electric charge in a gate capacitance;
a write bit line coupled to a gate electrode of the storage transistor;
a read bit line coupled to a drain electrode of the storage transistor; and
a switching element provided between the read bit line and a power supply;
wherein the switching element controls a potential of the read bit line so that in a standby state the read bit line stays in a floating state, and in a read operation state the potential of the read bit line becomes a power supply potential.
8. A semiconductor integrated circuit according to claim 7 , further comprising:
an access transistor for controlling conduction between the read bit line and the drain electrode of the storage transistor.
9. A semiconductor integrated circuit according to claim 7 , further comprising:
a write transistor for supplying the electric charge from the write bit line to the gate electrode of the storage transistor.
10. A semiconductor integrated circuit according to claim 9 ,
wherein a channel area of the write transistor is formed of a film having a film thickness of 5 nm or less.
11. A semiconductor integrated circuit according to claim 9 ,
wherein a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
12. A semiconductor integrated circuit according to claim 7 , further comprising:
a second memory cell provided with the switching element in common.
13. A semiconductor integrated circuit comprising:
a memory cell including a storage transistor for storing an electric charge in a gate capacitance;
a write bit line coupled to a gate electrode of the storage transistor;
a read bit line coupled to a drain electrode of the storage transistor; and
a switching element provided between a source electrode of the storage transistor and a power supply potential;
wherein in a standby state, a potential of the source of the storage transistor and a potential of the read bit line are controlled to become an equal potential.
14. A semiconductor integrated circuit according to claim 13 , further comprising:
an access transistor for controlling conduction between the read bit line and the drain electrode of the storage transistor.
15. A semiconductor integrated circuit according to claim 13 , further comprising:
a write transistor for supplying the electric charge from the write bit line to the gate electrode of the storage transistor.
16. A semiconductor integrated circuit according to claim 15 ,
wherein a channel area of the write transistor is formed of a film having a film thickness of 5 nm or less.
17. A semiconductor integrated circuit according to claim 16 ,
wherein a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
18. A semiconductor integrated circuit according to claim 13 , further comprising:
a second memory cell provided with the switching element in common.