Thin film transistor array panel having groups of proximately located thin film transistors and manufacturing method thereof

1. A thin film transistor array panel comprising:

a substrate;

a plurality of gate lines disposed on the substrate;

a plurality of data lines disposed on the substrate, wherein the plurality of gate lines and the plurality of data lines form a matrix pattern and wherein the gate lines and the data lines together define four pixels as a 2×2 matrix;

a plurality of thin film transistors in the pixels connected to the gate lines and the data lines, wherein each of the plurality of thin film transistors includes an organic semiconductor, wherein the plurality of thin film transistors comprises

a first thin film transistor is disposed in a lower right corner of the upper left pixel in the 2×2 matrix, a second thin film transistor is disposed in a lower left corner of the upper right pixel in the 2×2 matrix, a third thin film transistor is disposed in upper left corner of the lower right pixel in the 2×2 matrix, and a fourth thin film transistor is disposed in a upper right corner of the lower left pixel in the 2×2 matrix.

2. The thin film transistor array panel of claim 1 , wherein the organic semiconductors of the thin film transistors of at the least two adjacent pixels are separated.

3. The thin film transistor array panel of claim 1 , wherein the organic semiconductors of the thin-film transistors of the at least two adjacent pixels are joined.

4. The thin film transistor array panel of claim 1 , wherein two of the gate lines are disposed between two adjacent pixels in a single column, and wherein two of the data lines are disposed between two adjacent pixels in a single row.

5. The thin film transistor array panel of claim 4 , wherein the organic semiconductors of at the least two adjacent pixels are separated.

6. The thin film transistor array panel of claim 4 , wherein the organic semiconductors of at the least two adjacent pixels are made of one pattern.

7. The thin film transistor array panel of claim 4 , wherein the organic semiconductors include a soluble material.

8. The thin film transistor array panel of claim 7 , further comprising a plurality of gate insulators formed between the gate lines and the organic semiconductors,

wherein the gate insulators include a second soluble material.

9. The thin film transistor array panel of claim 8 , further comprising:

a lower partition disposed on the substrate; and

an upper partition disposed on the substrate;

wherein the gate insulators of the at least two adjacent pixels are disposed in at least one opening in the lower partition, and

wherein the organic semiconductors of the thin film transistors of the at least two adjacent pixels are disposed in at least one opening in the upper partition.

10. The thin film transistor array panel of claim 8 , further comprising a plurality of source electrodes connected to the data lines and a plurality of drain electrodes opposite the source electrodes with respect to the gate lines.

11. The thin film transistor array panel of claim 10 , wherein the drain electrodes and the source electrodes include indium tin oxide or indium zinc oxide.

12. The thin film transistor array panel of claim 10 , wherein the upper partition comprises an insulating layer formed on the source electrodes and the drain electrodes,

wherein the insulating layer includes a plurality of openings that exposes portions of the source and drain electrodes, and the organic semiconductors are formed in the openings that exposes the portions of the source and drain electrodes.

13. The thin film transistor array panel of claim 12 , wherein the openings of adjacent pixels are disposed proximate to one another.

14. The thin film transistor array panel of claim 1 , wherein adjacent pixels have inversion symmetry.