Data accessing interface having multiplex output module and sequential input module between memory and source to save routing space and power and related method thereof

1. A data accessing interface coupled between a memory and a source, comprising:

a multiplex output module, for outputting M bits of an N-bit digital data in each multiplexing operation to thereby output the N-bit digital data, wherein M and N are both positive integers, M is less than N, and

N

M

is a positive integer; and

a sequential input module, for sequentially latching data transmitted through M transmission lines to store the N-bit digital data;

wherein the multiplex output module comprises:

a buffer unit, for receiving the N-bit digital data from a complete row of the memory; and

a multiplex unit, coupled to the buffer unit, for selecting an M bit digital data out of a plurality of M-bit digital data comprised of the N-bit digital data stored in the buffer unit in each multiplexing operation and then outputting the plurality of M-bit digital data one by one, thereby outputting the N-bit digital data.

2. The data accessing interface of claim 1 , wherein the multiplex unit comprises M multiplexers, and

N

M

input nodes of each multiplexer are coupled to

N

M

specific latches in the buffer unit, respectively.

3. The data accessing interface of claim 1 , further comprising:

a control unit, coupled to the multiplex output module, for outputting a multiplex selection signal to the multiplex unit to control the multiplex unit to select an M-bit digital data out of the N-bit digital data periodically.

4. The data accessing interface of claim 1 , wherein the sequential input module comprises N latches, M input ports, and

N

M

latch control signals.

5. The data accessing interface of claim 4 , wherein when a first latch control signal is enabled, an M-bit digital data is stored into M latches through the M input ports; and remaining latch control signals are enabled sequentially to make all of the N-bit digital data stored into the N latches.

6. The data accessing interface of claim 1 , further comprising:

a control unit, for outputting a multiplex selection signal to the multiplex output module to control the multiplex output module to select an M-bit digital data out of the N-bit digital data periodically and for outputting

N

M

latch control signals to the sequential input module to control data latching of the sequential input module.

7. A data accessing method applied to a memory of an LCD display IC, comprising:

(a) providing a buffer unit in the memory for buffering an N-bit digital to be outputted in a row of the memory;

(b) utilizing a multiplexer to select an M-bit digital data out of the N-bit digital data stored in the buffer unit and then output the M-bit digital data; and

(c) repeatedly utilizing the multiplexer to output an M-bit digital data in each multiplexing operation until the number of times of outputting an M-bit digital data is equal to

N

M

,

thereby completely outputting the N-bit digital data stored in the row of the memory, wherein M and N are both positive integers, M is less than N, and

N

M

is a positive integer.

8. The data accessing method of claim 7 , wherein step (b) further comprises:

selecting an M-bit digital data out of the N-bit digital data in each multiplexing operation.