Audible noise reduction for single current shunt platform
A method and system for reducing audible motor noise in a system for reconstructing motor phase current from a DC bus current comprising current pulses on a DC bus in a PWM inverter motor drive system having a PWM cycle, and for controlling the motor, which forms a command voltage vector according to a space vector modulation arrangement for controlling the motor; measures the DC bus current on the DC bus supplying power to the inverter to reconstruct said motor phase current; and determines when the command voltage vector results in an inverter switching state that prevents the measuring of the DC bus current from accurately indicating motor phase current. During said inverter switching state, a current sampling scheduler applies a minimum pulse width constraint to said current pulses in said DC bus current to improve reconstruction of said motor phase current based on said DC bus current; and reduces the application of said minimum pulse width constraint to less than once per PWM cycle imposed by the PWM inverter motor drive system, thereby allowing motor phase current reconstruction with reduced audible motor noise. The current sampling scheduler synchronously samples said measured motor phase current to reduce errors in said measured motor phase current caused by said reduction of said minimum pulse constraint; reduces a bandwidth of said motor controller during said inverter switching state; and is adjustable in response to motor speed for setting the number of said minimum pulse width constraints per PWM cycle.
1. A method for reducing audible motor noise in a system for reconstructing motor phase current from a DC bus current comprising current pulses on a DC bus in a PWM inverter motor drive system having a PWM cycle, and for controlling the motor, comprising:
forming a command voltage vector according to a space vector modulation arrangement for controlling the motor;
measuring the DC bus current on the DC bus supplying power to the inverter to reconstruct said motor phase current;
determining a sector crossing region when the command voltage vector results in an inverter switching state that prevents the measuring of the DC bus current from accurately indicating motor phase current;
during said inverter switching state, applying a minimum pulse width constraint to said current pulses in said DC bus current to improve reconstruction of said motor phase current based on said DC bus current;
applying said minimum pulse width constraint less than once per PWM cycle during said sector crossing region, thereby allowing motor phase current reconstruction with reduced audible motor noise.
2. The method according to claim 1 , further comprising synchronously sampling said measured motor phase current to reject errors in said measured motor phase current caused by said reduction of said minimum pulse constraint during sector crossing.
3. The method according to claim 2 , further comprising reducing a bandwidth of said motor controller according to said sampling reduction in the sector crossing region.
4. The method according to claim 1 , further comprising reducing a bandwidth of said motor controller according to said sampling reduction in the sector crossing region.
5. The method according to claim 1 , wherein said current sampling scheduler is adjusted in response to motor speed for reducing the number of said minimum pulse width applications in the sector crossing region.
6. The method according to claim 5 , wherein in the reducing step, the reduction of said minimum pulse width applications is greater at slower motor speeds than at higher motor speeds.
7. A space vector PWM motor drive system having a noise reduction scheduler operated in accordance with the method of claim 1 .
8. A PWM inverter motor drive system for controlling a motor with audible motor noise reduction, comprising:
a motor controller having a PWM cycle and forming a command voltage vector according to a space vector modulation arrangement to be supplied to the motor;
a unit for measuring a DC bus current comprising current pulses on a DC bus supplying power to the inverter and reconstructing a motor phase current therefrom:
said motor controller determining a sector crossing region when the command voltage vector results in an inverter switching state that prevents the measuring of the DC bus current from accurately indicating motor phase current;
during said inverter switching state, a current sampling scheduler applying a minimum pulse width constraint to said current pulses in said DC bus current to improve reconstruction of said motor phase current based on said DC bus current;
said current sampling scheduler applying said minimum pulse width constraint less than once per PWM cycle during sector crossing, thereby allowing motor phase current reconstruction with reduced audible motor noise.
9. The system according to claim 8 , wherein said current sampling scheduler synchronously samples said measured motor phase current to reject errors in said measured motor phase current caused by said reduction of said minimum pulse constraint during sector crossing.
10. The system according to claim 9 , wherein said current sampling scheduler reduces a bandwidth of said motor controller in accordance with said sampling reduction in said sector crossing region.
11. The system according to claim 8 , wherein said current sampling scheduler reduces a bandwidth of said motor controller in accordance with said sampling reduction in said sector crossing region.
12. The system according to claim 8 , wherein said current sampling scheduler is adjustable in response to motor speed for reducing the number of said minimum pulse width applications in the sector crossing region.
13. The system according to claim 12 , wherein the reduction of said minimum pulse width applications is greater at slower motor speeds than at higher motor speeds.