Failure simulation based on system level boundary scan architecture
View Patent ↗A method and apparatus for reducing cost for the backplane and system test and for speeding up the time to market of a new product are disclosed. A failure simulation based on system level Boundary Scan architecture allows the use of an already available test infrastructure for test and validation.
1. An input/output (I/O) circuit pack for fault simulation, comprising:
an interface circuit for facilitating communications between a backplane boundary scan (BSCAN) bus and a local BSCAN chain; and
the local BSCAN chain comprising a plurality of BSCAN devices including a fault simulation device connected in series are adapted to cooperate with a test and validation system in an active mode of operation and to avoid operational contributions in an inactive mode of operation wherein the I/O circuit pack further comprises a plurality of failure simulation circuits providing fault simulation to a communication system.
2. The I/O circuit pack of claim 1 , wherein the plurality of failure simulation circuits comprises a watchdog circuit.
3. The I/O circuit pack of claim 1 , wherein the plurality of failure simulation circuit comprises small form factor pluggable (SFP) circuit.
4. The I/O circuit pack of claim 1 , wherein when the fault simulation device is simulating faults, the plurality of BSCAN devices on the I/O circuit pack in the local BSCAN chain are in a bypass state.
5. The I/O circuit pack of claim 1 , wherein the interface circuit comprises control signals, wherein the control signals communicate in parallel with the plurality of local BSCAN devices including the fault simulation device.
6. A method for fault simulation using existing test infrastructure of a test and validation system, comprising:
coupling an I/O circuit pack of failure simulation circuits providing fault simulation to the test and validaton system, the I/O circuit pack comprises an interface circuit for facilitating communications between a backplane boundary scan (BSCAN) bus and a local BSCAN chain, the local BSCAN chain comprising a plurality of BSCAN devices including a fault simulation device connected is series;
setting the fault simulation device to an active state, wherein the fault simulation device is adapted to cooperate with the test and validation system in an active state and to avoid operational contributions in an inactive state of operation; and
setting the plurality of BSCAN devices on the local BSCAN chain to a bypass state.
7. The method of claim 6 , wherein the plurality of failure simulation circuit comprises a watchdog circuit that is disabled to avoid a CPU recovery in case of software misbehavior.
8. The method of claim 6 , wherein the plurality of failure simulation circuit comprises a small form factor pluggable (SFP) that is switched off to simulate a broken fiber.
9. The method of claim 6 , wherein the test signal is serially transmitted to the plurality of BSCAN devices of the local BSCAN chain.
10. The method of claim 6 , wherein a control signal is transmitted to the fault simulation devices of the local BSCAN chain in parallel.
11. The method of claim 6 , wherein the I/O circuit pack functions as a slave circuit pack.
12. An apparatus comprising:
coupling means for facilitating communications between a plurality of failure simulation circuits providing fault simulation to a communication system;
an interface means for facilitating communications between a backplane boundary scan (BSCAN) bus and a local BSCAN chain means comprising a plurality of BSCAN devices including a fault simulation means connected in series; and
fault simulation means for cooperating with a test and validation system in an active mode of operation and to avoid operational contributions in an inactive mode of operation.
13. The apparatus of claim 12 , wherein the plurality of failure simulation circuits further comprises watchdog means.
14. The apparatus of claim 12 , wherein the plurality failure simulation circuits further comprises small form factor pluggable (SFP) means.
15. The apparatus of claim 12 , wherein when the fault simulation means is simulating faults, the plurality of BSCAN devices in the local BSCAN chain means are in a bypass state.
16. The apparatus of claim 12 , wherein the interface means provides control signals, wherein the control signals communicates in parallel with the plurality of BSCAN devices in the local BSCAN chain means.