IP Library Granted Patent US 7,636,409
Granted Patent B2
US 7,636,409 · App. 11/557,802 · Granted Dec 22, 2009

Digital phase locked loop for regenerating the clock of an embedded signal

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Quick Facts
Patent No.
US 7,636,409
App. No.
11/557,802
Granted
Dec 22, 2009
Kind
B2
Abstract

The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.

Claims (20)

1. A system for generating digital data bursts at a first clock rate, the system comprising: a receiver for acquiring a composite stream, determining a total number of audio samples per line in said acquired composite stream, wherein the total number of audio samples per line is varying, and determining the first clock rate, wherein determining the first clock rate includes using a total line width and the varying total number of audio samples in each line.

2. The system of claim 1 , further including a transmitter for forming said composite stream.

3. A method of generating data bursts at a first clock rate, said method comprising the steps of: forming a composite stream of audio and video data at a transmitter; acquiring said composite stream at a receiver; and determining the first clock rate for the data bursts from said composite stream at the receiver, wherein determining the first clock rate includes using a total line width and a number of audio samples in each line, wherein the number of audio samples per line is varying.

4. The method of claim 3 , including transmitting said composite stream at a second clock rate.

5. The method of claim 4 , wherein said second clock rate is greater than the first clock rate.

6. The method of claim 3 , including computing the average number of audio samples per line.

7. The method of claim 3 , including inserting audio data into video data forming said composite stream.

8. The method of claim 3 , including acquiring a width in data elements of a digital data burst.

9. The method of claim 3 , including acquiring a width in data elements of a data block of higher speed digital data.

10. The method of claim 3 , including computing a width of one period of a clock pulse at the first clock rate.

11. The system of claim 1 , wherein the composite stream is clocked at a second clock rate, wherein said second clock rate is greater than the first clock rate.

12. The system of claim 1 , wherein the receiver computes an average number of audio samples per line.

13. The system of claim 2 , wherein the transmitter inserts audio data into video data forming said composite stream.

14. The system of claim 1 , wherein the receiver acquires a width in data elements of a digital data burst.

15. The system of claim 1 , wherein the receiver acquires a width in data elements of a data block of higher speed digital data.

16. The system of claim 1 , wherein the receiver computes a width of one period of a clock pulse at the first clock rate.

17. The system of claim 1 , wherein the first clock rate is initially unknown.

18. The method of claim 3 , wherein the first clock rate is initially unknown.

19. The system of claim 6 , wherein the first clock rate is initially unknown.

20. The method of claim 12 , wherein the first clock rate is initially unknown.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →