Thin film transistor array panel
View Patent ↗A data line and an amorphous silicon pattern are formed on a substrate. The first electrode pattern is extended from the data line and overlaps an edge of the amorphous silicon pattern. The second electrode pattern is made of the same metal as the first electrode pattern and overlaps the edge of the amorphous silicon pattern at an opposite side of the first electrode pattern. Edges of the first and the second electrode patterns are sharply formed so that a tunneling effect easily occurs through the amorphous silicon pattern. An indium-tin-oxide pattern for a capacitor is formed at the end of the second electrode pattern. The capacitor is formed between the ITO pattern and a common electrode.
1. A thin film transistor (TFT) array panel, comprising:
a substrate divided into a display region and a peripheral region;
a gate wiring pattern formed on the substrate;
a first insulating film formed on the gate wiring pattern;
a data wiring pattern formed on the gate wiring pattern and comprising a first data line and a second data line;
a second insulating film formed on the data wiring pattern;
a first electrostatic discharge protection circuit comprising:
a first capacitor comprising a first electrode and a second electrode; and
a resistor comprising a first semiconductor pattern formed in the peripheral region, electrically connected between the first data line and the first electrode, wherein the first electrostatic discharge protection circuit has no control electrode generating an electric field for controlling conductivity of the first semiconductor pattern, and
wherein the data wiring pattern comprises the first electrode, and the gate wiring pattern comprises the second electrode; and
a third electrode formed on the second insulating film, electrically connected to the first electrode and overlapping the second electrode.
2. The TFT array panel of claim 1 , wherein the second insulating film has a contact hole exposing the first electrode, and the third electrode is connected to the first electrode through the contact hole.
3. The TFT array panel of claim 1 , wherein the first electrode partially overlaps the first semiconductor pattern.
4. The TFT array panel of claim 1 , wherein the second electrode is a dummy gate line.
5. The TFT array panel of claim 4 , wherein the data wiring pattern further comprises a dummy data line electrically connected to the dummy gate line.
6. The TFT array panel of claim 5 , fun her comprising an ohmic contact layer electrically coupled between the first semiconductor pattern and the first data line and between the first semiconductor pattern and the first electrode.
7. A thin film transistor (TFT) array panel, comprising:
a substrate divided into a display region and a peripheral region;
a gate wiring pattern formed on the substrate;
a data wiring pattern formed on the gate wiring pattern and comprising a first data line and a second data line;
a first electrostatic discharge protection circuit comprising:
a first capacitor comprising a first electrode and a second electrode; and
a resistor comprising a first semiconductor pattern formed in the peripheral region, electrically connected between the first data line and the first electrode, wherein the first electrostatic discharge protection circuit has no control electrode generating an electric field for controlling conductivity of the first semiconductor pattern; and
a second semiconductor pattern electrically coupled between the first electrode and the second data line neighboring the first data line.
8. The TFT array panel of claim 7 , wherein the second electrode is floated.
9. The TFT array panel of claim 8 , further comprising a second electrostatic discharge protection circuit comprising:
a second capacitor comprising a third electrode and the second electrode; and the second semiconductor pattern electrically coupled between the third electrode and the second data line.