IP Library Granted Patent US 7,984,301
Granted Patent B2
US 7,984,301 · App. 11/558,367 · Granted Jul 19, 2011

Bi-processor architecture for secure systems

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Quick Facts
Patent No.
US 7,984,301
App. No.
11/558,367
Granted
Jul 19, 2011
Kind
B2
Abstract

Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first CPU and the second CPU can communicate through a secure interface. The first CPU cannot access the sensitive information within the second CPU.

Claims (50)

1. A system comprising:

a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information;

a second CPU configured to perform tasks that manipulate the sensitive information on behalf of the first CPU;

a secure communication interface through which the first CPU and the second CPU communicate; and

where the first CPU cannot access the sensitive information within the second CPU and the first CPU has no access to processing methods within the second CPU through the secure communication interface.

2. The system of claim 1 where the second CPU includes one or more of:

a separate power source from the first CPU, a separate clock system from the first CPU, a separate program and data memory from the first CPU, dedicated analog sensors, or a hardware shield.

3. The system of claim 1 where:

the sensitive information is one or more cryptographic keys.

4. The system of claim 1 where:

data sent over the secure communication interface is encrypted or digitally signed.

5. The system of claim 1 where:

the first CPU is unable to directly control the second CPU through the secure communication interface.

6. A system comprising:

a first central processing unit (CPU);

a second CPU where the second CPU includes a separate power source and a separate memory from the first CPU;

a secure communication interface through which the first CPU and the second CPU communicate where the first CPU has no access to processing methods within the second CPU through the secure communication interface; and

where the first CPU cannot access information in the separate memory.

7. The system of claim 6 where the second CPU includes:

a separate clock system from the first CPU.

8. The system of claim 6 where:

data sent over the secure communication interface is encrypted or digitally signed.

9. The system of claim 6 where:

the separate memory contains one or more cryptographic keys.

10. The system of claim 9 where:

the first CPU can provide encrypted information to the second CPU which the second CPU can decrypt using the one or more cryptographic keys.

11. A method comprising:

receiving an external communication at a first Central Processing Unit (CPU);

determining by the first CPU that the external communication requires manipulation of sensitive information; and

employing a secure CPU by the first CPU by way of a secure communication interface to process the external communication, where the first CPU has no access to processing methods within the secure CPU through the secure communication interface.

12. The method of claim 11 where the secure CPU includes one or more of:

a separate power source from the first CPU, a separate clock system from the first CPU, a separate program and data memory from the first CPU, dedicated analog sensors, or a hardware shield.

13. The method of claim 11 where:

the sensitive information is one or more cryptographic keys.

14. The method of claim 11 where:

data sent over the secure communication interface is encrypted or digitally signed.

15. The method of claim 11 where:

the first CPU is unable to directly control the secure CPU through the secure communication interface.

16. A computer program product, encoded on a non-transitory computer-readable medium, operable to cause data processing apparatus to perform operations comprising:

receiving an external communication at a first Central Processing Unit (CPU);

determining by the first CPU that the external communication requires manipulation of sensitive information; and

employing a secure CPU by the first CPU by way of a secure communication interface to process the external communication, where the first CPU has no access to processing methods in the secure CPU through the secure communication interface.

17. The computer program product of claim 16 where the secure CPU includes one or more of:

a separate power source from the first CPU, a separate clock system from the first CPU, a separate program and data memory from the first CPU, dedicated analog sensors, or a hardware shield.

18. The computer program product of claim 16 where:

the sensitive information is one or more cryptographic keys.

19. The computer program product of claim 16 where:

data sent over the secure communication interface is encrypted or digitally signed.

20. The computer program product of claim 16 where:

the first CPU is unable to control the secure CPU through the secure communication interface.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2019
From: VERIMATRIX
To: RAMBUS INC.
Reel/Frame 051262/0413 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Nov 21, 2019
From: GLAS SAS, AS AGENT
To: INSIDE SECURE
Reel/Frame 051076/0306 →
CHANGE OF ADDRESS Recorded Oct 16, 2019
From: VERIMATRIX
To: VERIMATRIX
Reel/Frame 050733/0003 →
CHANGE OF NAME Recorded Oct 7, 2019
From: INSIDE SECURE
To: VERIMATRIX
Reel/Frame 050647/0428 →
SECURITY INTEREST Recorded Feb 27, 2019
From: INSIDE SECURE
To: GLAS SAS, AS SECURITY AGENT
Reel/Frame 048449/0887 →
CHANGE OF ADDRESS Recorded Aug 25, 2016
From: INSIDE SECURE
To: INSIDE SECURE
Reel/Frame 040116/0700 →
CHANGE OF NAME Recorded Sep 5, 2012
From: INSIDE CONTACTLESS
To: INSIDE SECURE
Reel/Frame 028901/0685 →