Memory with increased write margin bitcells
View Patent ↗A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.
1. A memory, comprising:
a first bit line;
a second bit line;
a first word line;
a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal;
a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters;
a first pass transistor coupled to the first word line, the first input/output node, and the first bit line; and
a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.
2. The memory of claim 1 , further comprising a load coupled between the second power supply terminal and the second power supply node.
3. The memory of claim 2 , wherein the load comprises a diode-connected transistor.
4. The memory of claim 1 , wherein the first pair of cross-coupled inverters comprises;
a first N channel transistor having a gate coupled to the first input/output node, a drain coupled to the second input/output node; and a source coupled to the first power supply terminal;
a second N channel transistor having a gate coupled to the second input/output node, a drain coupled to the first input/output node; and a source coupled to the first power supply node;
a first P channel transistor having a gate coupled to the first input/output node, a drain coupled to the second input/output node; and a source coupled to the second power supply node; and
a second P channel transistor having a gate coupled to the second input/output node, a drain coupled to the first input/output node; and a source coupled to the second power supply node.
5. The memory of claim 1 , wherein the gating transistor receives the first write enable signal via the word line.
6. The memory of claim 1 , further comprising a first write enable line for carrying the first write enable signal coupled to the first gating transistor.
7. The memory of claim 6 , further comprising a first signal generator coupled to the first write enable line for generating the first write enable signal.
8. The memory of claim 6 , further comprising:
a third bit line;
a fourth bit line;
a second pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to the first power supply terminal;
a second gating transistor coupled between the second power supply terminal and the second power supply node of the second pair of cross-coupled inverters;
a third pass transistor coupled to the first word line, the first input/output node of the second pair of cross-coupled inverters, and the third bit line;
a fourth pass transistor coupled to the first word line, the second input/output node of the second pair of cross-coupled inverters, and the fourth bit line;
a third gating transistor coupled between the second power supply node of the first pair of cross-coupled inverters and the second power supply terminal;
a first column select line substantially parallel to the first, second, third, and fourth bit lines that is coupled to the third gating transistor;
a fourth gating transistor coupled between the second power supply node of the second pair of cross-coupled inverters and the second power supply terminal; and
a second column select line substantially parallel to the first, second, third, and fourth bit lines that is coupled to the fourth gating transistor;
wherein the first and third gating transistors are gated to a non-conductive condition during a write of the first pair of cross-coupled inverters, and the second and fourth gating transistors are gated to a non-conductive condition during a write of the second pair of cross-coupled inverters.
9. The memory of claim 6 , further comprising:
a second word line;
a second pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to the first power supply terminal;
a second gating transistor coupled between the second power supply terminal and the second power supply node of the second pair of cross-coupled inverters;
a third pass transistor coupled to the second word line, the first input/output node of the second pair of cross-coupled inverters, and the first bit line;
a fourth pass transistor coupled to the second word line, the second input/output node of the second pair of cross-coupled inverters, and the second bit line;
a third gating transistor coupled between the second power supply node of the first pair of cross-coupled inverters and the second power supply terminal;
a fourth gating transistor coupled between the second power supply node of the second pair of cross-coupled inverters and the second power supply terminal; and
a first column select line substantially parallel to the first and second bit lines that is coupled to the third gating transistor and the fourth gating transistor;
wherein the first column select line gates the third gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters, and gates the fourth gating transistor to a non-conductive condition during a write of the second pair of cross-coupled inverters.
10. The memory of claim 9 , further comprising:
a third bit line;
a fourth bit line;
a third pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to the first power supply terminal;
a fifth gating transistor coupled between the second power supply terminal and the second power supply node of the third pair of cross-coupled inverters;
a sixth gating transistor coupled between the second power supply terminal and the second power supply node of the third pair of cross-coupled inverters;
a fifth pass transistor coupled to the first word line, the first input/output node of the third pair of cross-coupled inverters, and the third bit line;
a sixth pass transistor coupled to the first word line, the second input/output node of the third pair of cross-coupled inverters, and the fourth bit line;
a second column select line substantially parallel to the first, second, third, and fourth bit lines that is coupled to the sixth gating transistor;
wherein the fifth and sixth gating transistors are gated to a non-conductive condition during a write of the third pair of cross-coupled inverters.
11. The memory of claim 1 , further comprising:
a third bit line;
a fourth bit line;
a second word line;
a third pass transistor coupled to the second word line, the first input/output node, and the third bit line; and
a fourth pass transistor coupled to the second word line, the second input/output node, and fourth bit line.
12. In a memory comprising a first pair of cross-coupled inverters, a first pair of bit lines, a first pair of pass gates coupled between the first pair of bit lines and the first pair of cross-coupled inverters, and a first word line coupled to the first pair of pass gates, a method comprising:
applying a power supply voltage to the first pair of cross-coupled inverters to retain data in the first pair of cross-coupled inverters;
enabling the first word line during writing of the first pair of cross-coupled inverters;
applying data to the first pair of bit lines during writing of the first pair of cross-coupled inverters; and
selectively decoupling the power supply voltage from the first pair of cross-coupled inverters during writing of the first pair of cross-coupled inverters.
13. The method of claim 12 , further comprising:
disabling the first word line to terminate writing of the first pair of cross-coupled inverters; and
restoring the power supply voltage to the first pair of cross-coupled inverters prior to the step of disabling the first word line.
14. In the method of claim 12 , wherein the memory further comprises a second word line, a second pair of bit lines, and a second pair of pass transistors coupled to the second word lines and between the second pair of bit lines and the first pair of cross-coupled inverters, the method further comprising:
enabling the second word line during writing of the first pair of cross-coupled inverters;
applying data to the second pair of bit lines during writing of the first pair of cross-coupled inverters; and
decoupling the power supply voltage from the first pair of cross-coupled inverters during the steps of enabling the second word line and applying data to the second pair of bit lines.
15. The method of claim 12 , wherein the step of decoupling is further characterized as retaining a different voltage from the power supply voltage to the first pair of cross-coupled inverters.
16. In the method of claim 12 , wherein the memory further comprises a second pair of cross-coupled inverters, a second pair of bit lines, a second pair of pass transistors that are coupled to the first word line and between the second pair of bit lines and the second pair of cross-coupled inverters, the method further comprising:
applying a power supply voltage to the second pair of cross-coupled inverters to retain data in the second pair of cross-coupled inverters;
enabling the first word line during writing of the second pair of cross-coupled inverters;
applying data to the second pair of bit lines during writing of the second pair of cross-coupled inverters;
decoupling the power supply voltage from the second pair of cross-coupled inverters during writing of the second pair of cross-coupled inverters; and
retaining applying the power supply voltage to the first pair of cross-coupled inverters throughout the writing of the second pair of cross-coupled inverters.
17. In the method of claim 12 , wherein the memory further comprises a second pair of cross-coupled inverters, a second word line, a second pair of pass transistors that are coupled to the second word line and between the first pair of bit lines and the second pair of cross-coupled inverters, the method further comprising:
applying a power supply voltage to the second pair of cross-coupled inverters to retain data in the second pair of cross-coupled inverters;
enabling the second word line during writing of the second pair of cross-coupled inverters;
applying data to the first pair of bit lines during writing of the second pair of cross-coupled inverters;
decoupling the power supply voltage from the second pair of cross-coupled inverters during writing of the second pair of cross-coupled inverters; and
retaining applying the power supply voltage to the first pair of cross-coupled inverters throughout the writing of the second pair of cross-coupled inverters.
18. The method of claim 16 , wherein enabling the first word line during writing of the first pair of cross-coupled inverters comprises processing at least two different write enable signals.
19. A memory, comprising:
a word line;
a plurality of memory cells coupled to the word line;
a plurality of pairs of bit lines, wherein each memory cell of the plurality of memory cells is coupled to a different pair of bit lines of the plurality of bit lines;
power means for coupling power to the memory cells for retaining states of the memory cells and decoupling power from the plurality of memory cells during a write of the plurality of memory cells.
20. The memory of claim 19 , wherein the power means comprises:
a plurality of gating transistors, wherein each memory cell of the plurality of memory cells has coupled thereto a different one of the gating transistors of the plurality of gating transistors;
a signal generator for generating a write enable signal; and
a write enable line coupled to the signal generator and the plurality of gating transistors.
21. A memory, comprising:
a first bit line;
a second bit line;
a first word line;
a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal;
a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor being non-conductive in response to a control signal;
a first pass transistor coupled to the first word line, the first input/output node, and the first bit line; and
a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.
22. The memory of claim 21 , wherein the control signal is used during a write operation.
23. The memory of claim 21 , wherein the control signal is used during a standby operation.
24. The memory of claim 21 , wherein the control signal is coupled to the first word line.
25. The memory of claim 23 , wherein during the standby operation the control signal is used to decouple the first power supply node from the first power supply terminal.