IP Library Granted Patent US 7,987,451
Granted Patent B1
US 7,987,451 · App. 11/561,809 · Granted Jul 26, 2011

System, method and computer program product for verifying invocations of interfaces

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,987,451
App. No.
11/561,809
Granted
Jul 26, 2011
Kind
B1
Abstract

A verification system, method and computer program product are provided. In one embodiment, one of a plurality of call instruction formats is selected. In addition, it is verified whether an invocation of an interface was attempted by code utilizing the selected call instruction format. Further, the selection and the verification are repeated for each of the plurality of call instruction formats. In another embodiment, a return target address is identified. Still yet, it is determined whether return of contra to the return target address would result in invocation a one of a plurality of interfaces.

Claims (35)

1. A method, comprising:

selecting one of a plurality of call instruction formats; and

verifying whether an invocation of an interface was attempted by code utilizing the selected call instruction format, utilizing a processor;

wherein the selecting and verifying are repeated for each of the plurality of call instruction formats.

2. The method of claim 1 , and further comprising intercepting the invocation of the interface.

3. The method of claim 1 , and further comprising storing the code that attempted the invocation of the interface.

4. The method of claim 1 , wherein the code is identified utilizing a return address associated with the attempted invocation.

5. The method of claim 4 , wherein a target address associated with the code is identified based on the return address and the selected call instruction format.

6. The method of claim 5 , wherein the verifying further includes determining whether the target address matches an address associated with the interface.

7. The method of claim 6 , wherein the attempted invocation of the interface is conditionally allowed to continue based on the determination.

8. The method of claim 5 , wherein a jump instruction associated with the target address is identified.

9. The method of claim 8 , wherein the verifying further includes determining whether a jump target address associated with the jump instruction matches an address associated with the interface.

10. The method of claim 1 , wherein each of the plurality of the call instruction formats includes a template.

11. The method of claim 10 , wherein each template defines a length of a call instruction.

12. A computer program product embodied on a non-transitory computer readable medium, comprising:

computer code for selecting one of a plurality of call instruction formats; and

computer code for verifying whether an invocation of an interface was attempted by code utilizing the selected call instruction format;

wherein the computer program product is operable such that the selecting and verifying are repeated for each of the plurality of call instruction formats.

13. A system, comprising:

a processor for selecting one of a plurality of call instruction formats, the processor further adapted for verifying whether an invocation of an interface was attempted by code utilizing the selected call instruction format;

wherein the system is operable such that the selecting and verifying are repeated for each of the plurality of call instruction formats.

14. The system of claim 13 , further comprising a display and memory coupled to the processor via a bus.

15. A method, comprising:

identifying a return target address; and

determining whether return of control to the return target address would result in invocation of one of a plurality of interfaces, utilizing a processor.

16. The method of claim 15 , and further comprising skipping a plurality of instructions pointed to by the return target address.

17. The method of claim 16 , wherein the plurality of instructions include no operation instructions.

18. The method of claim 15 , and further comprising identifying an additional return target address.

19. The method of claim 18 , wherein the determining further includes determining whether the additional return target address matches an address associated with one of the plurality of interfaces.

20. The method of claim 15 , wherein invocation of an interface by code associated with the return target address is intercepted.

21. The method of claim 15 , wherein invocation of an interface by code associated with the return target address is conditionally allowed to continue based on the determination.

22. The method of claim 15 , wherein the plurality of interfaces are stored in a watch list.

23. The method of claim 15 , wherein a violation event is conditionally performed based on the determination.

24. The method of claim 15 , wherein a jump instruction associated with the additional return target address is identified.

25. The method of claim 24 , wherein the determining further includes determining whether a jump target address associated with the jump instruction matches an address associated with one of the plurality of interfaces.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE PATENT TITLES AND REMOVE DUPLICATES IN THE SCHEDULE PREVIOUSLY RECORDED AT REEL: 059354 FRAME: 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 23, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 060792/0307 →
SECURITY INTEREST Recorded Mar 3, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
Reel/Frame 059354/0335 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045056/0676 Recorded Mar 2, 2022
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 059354/0213 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045055/0786 Recorded Oct 26, 2020
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 054238/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045056 FRAME 0676. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 054206/0593 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045055 FRAME 786. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 055854/0047 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 045056/0676 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 045055/0786 →
CHANGE OF NAME AND ENTITY CONVERSION Recorded Aug 24, 2017
From: MCAFEE, INC.
To: MCAFEE, LLC
Reel/Frame 043665/0918 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2006
From: DALCHER, GREGORY WILLIAM
To: MCAFEE, INC.
Reel/Frame 018546/0017 →