PSK receiver, PSK demodulating circuit, communication apparatus, and PSK receiving method
A phase-shift keying (PSK) receiver includes a carrier wave generator generating a carrier wave, an extracting unit extracting an in-phase component I and a quadrature component Q from a received signal on the basis of the carrier wave and the received signal, a comparator comparing the in-phase component I and the quadrature component Q extracted from the received signal to a predetermined threshold values respectively and acquiring 1-bit digital signals corresponding to the in-phase component I and the quadrature component Q respectively; and a BPSK demodulator demodulating the received signal using a binary phase-shift keying (BPSK) scheme on the basis of positional relationship on I-Q constellation between the 1-bit digital signals corresponding to the in-phase component I and the quadrature component Q acquired by the comparator.
1. A phase-shift keying (PSK) receiver, comprising:
a quadrant determining circuit that determines a quadrant on an I-Q constellation where a phase point defined by 1-bit digital signals respectively corresponding to an in-phase component I and an quadrature component Q included in a received signal exists;
a rotating direction determining circuit that determines rotating direction of the phase point defined by the in-phase component I and the quadrature component Q included in the received signal;
an IQ determining circuit that compensates the in-phase component I and the quadrature component Q by determining whether the in-phase component I and the quadrature component Q included in the received signal are right or not on the basis of the determination result in the quadrant determining circuit and the rotating direction determining circuit;
a state determining circuit that determines position on the I-Q constellation of the phase point; and
a determining circuit that demodulates the received signal on the basis of the compensation result in the IQ determining circuit and the determination result in the state determining circuit,
wherein the state determining circuit divides the I-Q constellation into a first domain including a first quadrant and a third quadrant excluding predetermined range from I axis and Q axis, on a second domain including a second quadrant and a fourth quadrant excluding the predetermined range from the I axis and Q axis, on a third domain including the predetermined range from the Q axis, and on a fourth domain within the predetermined range from the I axis,
wherein the in-phase component I and the quadrature component Q included in the received signal are not matched, the state determining circuit determines that the present domain of the phase points is changed to the next domain along the rotating direction determined by the rotating direction determining circuit, and
wherein the state determining circuit stops observing the quadrant on which the corresponding phase point stays at the moment after the time while the state determining circuit continues to observe passes, and outputs the determination result representing the domain on which the corresponding phase point stay, on the basis of the observation result during the observing time after waiting time of waiting the output of the determination result passes.
2. The PSK receiver according to claim 1 , further comprising: a frequency offset detecting circuit detecting a frequency offset of a carrier wave,
wherein the state determining circuit sets the observation time and the waiting time matching to the frequency offset value detected in the frequency offset detecting circuit.
3. The PSK receiver according to claim 1 , wherein the state determining circuit recognizes staying time when the corresponding phase point remains on the one domain on the basis of the output of the quadrant determining circuit, sets the observation time relatively longer when the corresponding staying time is rather long, and sets the observation time relatively shorter when the corresponding staying time is rather short.
4. The PSK receiver according to claim 1 , wherein the state determining circuit recognizes staying time when the corresponding phase point remains on the one domain on the basis of the output of the quadrant determining circuit, sets the waiting time relatively longer when the corresponding staying time is rather long, and sets the waiting time relatively shorter when the corresponding staying time is rather short.
5. The PSK receiver according to claim 1 , which repeats the operation in which the state determining circuit recognizes staying time when the corresponding phase point remains on the one domain on the basis of the output of the quadrant determining circuit, sets the waiting time relatively longer when the corresponding staying time is rather long and the observing time as the predetermined initial value, and sets the observing time relatively longer and returns the waiting time to the predetermined initial value after the waiting time set longer reaches the predetermined upper limit, and sets the waiting time relatively shorter when the corresponding staying time is rather short and the observing time as the predetermined initial value, and sets the observing time relatively shorter and returns the waiting time to the predetermined initial value when the waiting time set shorter reaches the predetermined lower limit.