Integrated circuit and method of manufacturing the same
View Patent ↗An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode. At least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted. The implantation region has the first conductivity type impurity and the second conductivity type impurity. Further, the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.
1. An integrated circuit, comprising:
a semiconductor substrate that has a first well region and a second well region containing p-type impurity at a first concentration;
an enhancement type MOS transistor formed in the first well region and having a first channel region under a first gate electrode; and
a depletion type MOS transistor formed in the second well region and having a second channel region under a second gate electrode,
wherein in a surface region of the first channel region, a first layer is formed that contains a p-type impurity at a second concentration,
in a surface region of the second channel region, a second layer is formed that contains an n-type impurity at a third and a p-type impurity at a fourth concentration,
the fourth concentration is the same as the first concentration and the second concentration is higher than the first concentration, and
wherein in the second channel region, second p-type pocket implantation regions are provided under and directly contact the second layer; and in the first channel region, first p-type pocket implantation regions are provided under and directly contact the first layer.
2. A solid-state imaging device comprising an integrated circuit as claimed in claim 1 .
3. The integrated circuit according to claim 1 ,
wherein the n-type impurity contained in the second layer is phosphorus or arsenic.
4. The integrated circuit according to claim 1 ,
wherein in the first and second channel regions, the first layer and the second layer are formed, respectively, in a surface region of the semiconductor substrate.
5. The solid-state imaging device according to claim 2 ,
wherein in the first and second channel regions, the first layer and the second layer are formed, respectively, in a surface region of the semiconductor substrate.
6. The integrated circuit according to claim 1 , wherein the p-type impurity contained in the first layer is boron.
7. The integrated circuit according to claim 1 further comprising, a first channel stop region formed in the first well region.
8. The integrated circuit according to claim 1 further comprising, a second channel stop region formed in the second welt region.
9. The integrated circuit according to claim 1 further comprising, a first sidewall formed on a side of the first gate electrode.
10. The integrated circuit according to claim 1 further comprising, a second sidewall formed on a side of the second gate electrode.
11. The integrated circuit according to claim 1 further comprising first LDD regions formed on sides of the first channel region, respectively.
12. The integrated circuit according to claim 1 further comprising, second LDD regions formed on sides of the second channel region, respectively.
13. The integrated circuit according to claim 11 further comprising, first source/drain regions formed on outsides of the rust LDD regions, respectively.
14. The integrated circuit according to claim 12 further comprising, second source/drain regions formed on outsides of the second LDD regions, respectively.
15. The integrated circuit according to claim 11 , wherein in the first channel region, first p-type pocket implantation regions are provided under the first LDD regions.
16. The integrated circuit according to claim 12 , wherein in the second channel region, second p-type pocket implantation regions are provided under the second LDD regions.
17. The integrated circuit according to claim 13 , wherein in the first channel region, first p-type pocket implantation regions are provided under the first source/drain regions.
18. The integrated circuit according to claim 14 , wherein in the second channel region, second p-type pocket implantation regions are provided under the second source/drain regions.