IP Library Granted Patent US 7,761,739
Granted Patent B2
US 7,761,739 · App. 11/562,591 · Granted Jul 20, 2010

Method for checkpointing a system already engaged in a concurrent checkpoint

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Quick Facts
Patent No.
US 7,761,739
App. No.
11/562,591
Granted
Jul 20, 2010
Kind
B2
Abstract

Concurrent checkpointing for rollback recovery for system failures is disclosed. The system includes a stable database, and a processor configured to receive and process a checkpoint request while a first thread performs a process and a second thread stores contents of memory regions listed in a first list to the stable storage. Processing the checkpoint request includes write protecting all memory regions listed in a previously initialized and populated second list, initializing an empty third list, creating a coalesced list by combining the contents of the first and second lists, and assigning the coalesced list to the second thread while the first thread proceeds with the process.

Claims (55)

1. A storage medium containing a set of program instructions executable by a processor within a system, comprising:

a routine to receive a checkpoint request while a first thread performs a process and while a second thread performs a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to stable storage;

a routine to determine that the size of the first list is less than a tolerance value;

a routine to write protecting all memory regions listed in a previously initialized and populated second list, and initialize an empty third list, in response to the determination;

a routine to create a coalesced list by combining the contents of the first and second lists, and assign the coalesced list to the second thread while the first thread proceeds with the process; and

a routine to increment the size of the first list.

2. The storage medium of claim 1 wherein the size of the first list comprises the number of times the first list has been coalesced with other lists.

3. The storage medium of claim 1 further comprising a routine to receive notification that the first thread needs write access to a memory region, add the memory region to the third list, determine that the memory region is not listed in the coalesced list, and remove write protection from the memory region.

4. The storage medium of claim 1 further comprising a routine to receive notification that the first thread needs write access to a memory region, add the memory region to the third list, determine that the memory region is listed in the coalesced list, access the second thread and cause it to record the contents of the memory region to stable storage immediately, and remove write protection from the memory region.

5. A storage medium containing a set of program instructions executable by a processor within a system, comprising:

a routine to receive a checkpoint request while a first thread performs a process and while a second thread implements a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to stable storage; and

a routine to determine that the size of the first list exceeds a tolerance value; and a routine to block processing by the first thread in response to the determination.

6. The storage medium of claim 5 further comprising:

a routine to allow the second thread to record in stable storage the contents of all the memory regions listed in the first list while the first thread is blocked; and

a routine to receive notification that the first list is empty and allowing processing by the first thread to proceed.

7. A computer system, comprising: a communications output communicatively connected to stable storage; and

a processor configured to receive a checkpoint request while a first thread performs a process and while a second thread implements a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to the stable storage;

the processor further configured to write protect all memory regions listed in a previously initialized and populated second list and to initialize an empty third list;

the processor further configured to create a coalesced list by combining the contents of the first and second lists; and

the processor further configured to assign the coalesced list to the second thread while the first thread proceeds with the process.

8. The computer system of claim 7 wherein the processor is further configured to direct the second thread to record the contents of memory regions listed in the coalesced list to the stable storage and remove those memory regions from the coalesced list.

9. The computer system of claim 7 wherein the processor is further configured to receive notification that the first thread needs write access to a memory region and, in response to the notification, add the memory region to the third list, and wherein the processor is further configured to determine that the memory region is not listed in the coalesced list and, in response to the determination, remove write protection from the memory region.

10. The computer system of claim 7 wherein the processor is further configured to receive notification that the first thread needs write access to a memory region and, in response to the notification, add the memory region to the third list, and wherein the processor is further configured to determine that the memory region is listed in the coalesced list and, in response to the determination, record the contents of the memory region to stable storage immediately and remove write protection from the memory region.

11. A computer system, comprising: a communications output communicatively connected to stable storage; and

a processor configured to receive a checkpoint request while a first thread performs a process and while a second thread implements a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to the stable storage;

the processor further configured to determine that the size of the first list is less than a tolerance value and, in response to the determination, write protect all memory regions listed in a previously initialized and populated second list and initialize an empty third list;

the processor further configured to create a coalesced list by combining the contents of the first and second lists, and assign the coalesced list to the second thread while the first thread proceeds with the process; and

the processor further configured to increment the size of the first list.

12. The computer system of claim 11 wherein the processor is further configured to receive notification that the first thread needs write access to a memory region, add the memory region to the third list, determine that the memory region is not listed in the coalesced list, and remove write protection from the memory region.

13. The computer system of claim 11 wherein the processor is further configured to receive notification that the first thread needs write access to a memory region, add the memory region to the third list, determine that the memory region is listed in the coalesced list, record the contents of the memory region to stable storage immediately, and remove write protection from the memory region.

14. A computer system, comprising:

a communications output communicatively connected to stable storage; and

a processor configured to receive a checkpoint request while a first thread performs a process and while a second thread implements a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to the stable storage; and

wherein the processor is further configured to determine that the size of the first list exceeds a tolerance value and, in response to the determination, block processing by the first thread.

15. The computer system of claim 14 wherein the processor is further configured to allow the second thread to record in stable storage the contents of all the memory regions listed in the first list while the first thread is blocked; and

wherein the processor is further configured to allow processing by the first thread to proceed upon receipt of notification that the first list is empty.

16. A method of checkpointing a system, comprising:

receiving a checkpoint request while a first thread performs a process and while a second thread implements a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to stable storage and, in response to the receipt, write protecting all memory regions listed in a previously initialized and populated second list;

initializing an empty third list; and

creating a coalesced list by combining the contents of the first and second lists, and assigning the coalesced list to the second thread while the first thread proceeds with the process.

17. A processor, comprising:

means for receiving a checkpoint request while a first thread performs a process and while a second thread implements a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to stable storage;

means for write protecting all memory regions listed in a previously initialized and populated second list;

means for initializing an empty third list;

means for creating a coalesced list by combining the contents of the first and second lists; and

means for assigning the coalesced list to the second thread while the first thread proceeds with the process.

18. A storage medium containing a set of program instructions executable by a processor within a system, comprising:

a routine for receiving a first checkpoint request while a first thread is implementing a process and while a second thread is implementing a second checkpoint concurrently, the second checkpoint comprising storing contents of memory regions listed in a first list to stable storage;

a routine to write protect all memory regions listed in a previously initialized and populated second list;

a routine to initialize an empty third list;

a routine to create a coalesced list by combining the contents of the first and second lists; and

a routine to assign the coalesced list to the second thread while the first thread proceeds with the process.

19. The storage medium of claim 18 wherein the second thread records the contents of memory regions listed in the coalesced list to stable storage and removes those memory regions from the coalesced list.

20. The storage medium of claim 18 further comprising a routine to receive notification that the first thread needs write access to a memory region, add the memory region to the third list, determine that the memory region is not listed in the coalesced list, and remove write protection from the memory region.

21. The storage medium of claim 18 further comprising a routine to receive notification that the first thread needs write access to a memory region, add the memory region to the third list, determine that the memory region is listed in the coalesced list, record the contents of the memory region to stable storage immediately, and remove write protection from the memory region.

Assignments (7)
RELEASE OF COLLATERAL UNDER SECURITY AGREEMENT Recorded Aug 29, 2012
From: TRIPLEPOINT CAPITAL LLC
To: LIBRATO, INC.
Reel/Frame 028884/0584 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2012
From: LIBRATO, INC.
To: OPEN INVENTION NETWORK, LLC
Reel/Frame 028677/0154 →
CHANGE OF NAME Recorded Aug 12, 2010
From: EVERGRID, INC.
To: LIBRATO, INC.
Reel/Frame 024831/0872 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RE-RECORDING TO REMOVE INCORRECT APPLICATIONS. PLEASE REMOVE 12/420,015; 7,536,591 AND PCT US04/38853 FROM PROPERTY LIST. PREVIOUSLY RECORDED ON REEL 023538 FRAME 0248. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME SHOULD BE - ASSIGNOR: CALIFORNIA DIGITAL CORPORATION; ASSIGNEE: EVERGRID, INC.. Recorded Jul 22, 2010
From: CALIFORNIA DIGITAL CORPORATION
To: EVERGRID, INC.
Reel/Frame 024726/0876 →
CHANGE OF NAME Recorded Nov 18, 2009
From: CALIFORNIA DIGITAL CORPORATION; EVERGRID, INC.
To: LIBRATO, INC.
Reel/Frame 023538/0248 →
SECURITY AGREEMENT Recorded Jul 29, 2008
From: EVERGRID, INC.
To: TRIPLEPOINT CAPITAL LLC
Reel/Frame 021308/0437 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2007
From: RUSCIO, JOSEPH F; HEFFNER, MICHAEL A
To: EVERGRID, INC.
Reel/Frame 018958/0253 →