Display control circuit
View Patent ↗A display control circuit includes a driver circuit DR which drives a plurality of pixels, and a driver control circuit which controls the driver circuit. The driver control circuit includes a control bus which transfers instruction data, an operation setting unit which executes operation settings in accordance with the instruction data from the control bus, and a gateway unit provided for a case in which the instruction data is internally generated and output to the control bus, and is capable of enabling or disabling an instruction data output to the control bus in accordance with a control input signal.
1. A display control circuit comprising:
a driver circuit which drives a plurality of pixels; and
a driver control circuit which controls said driver circuit,
wherein said driver control circuit includes
a control bus which transfers instruction data,
an operation setting unit which executes operation settings in accordance with the instruction data from said control bus,
an internal processor which supplies the instruction data for said operation setting unit via the control bus, and
a gateway unit which is provided between said control bus and said internal processor, and includes a control input terminal receiving a control input signal from a detachable external processor capable of controlling the operation setting unit, the gateway unit disabling an instruction data output from the internal processor to the control bus in accordance with the control bus signal from the external processor when the external processor is connected to the control bus,
wherein said control bus includes a data bus for transferring a packet signal of the instruction data, and a clock bus for transferring a clock signal for extracting the instruction data from the packet signal, and
wherein said gateway unit further includes a packet signal output buffer which outputs the packet signal to said data bus, and a clock signal output buffer which outputs the clock signal to said clock bus, and said packet signal output buffer and said clock signal output buffer are kept in a high-impedance output state in accordance with the control input signal received from said external processor via said control input terminal when the external processor is connected to the control bus.
2. The display control circuit according to claim 1 , wherein said driver control circuit includes an image processing circuit, a vertical timing control circuit, a horizontal timing control circuit, a common voltage generating circuit, and a reference gradation voltage generating circuit, and said operation setting unit is configured to execute an operation setting of at least one of said image processing circuit, said vertical timing control circuit, said horizontal timing control circuit, said common voltage generating circuit, and said reference gradation voltage generating circuit.