Thin film transistor array panel and method of manufacturing the same
View Patent ↗The present invention provides a thin film transistor array panel which includes a substrate, gate lines formed on the substrate, polycrystalline semiconductors formed on the gate lines, data lines formed on the polycrystalline semiconductors and including first electrodes, second electrodes formed on the polycrystalline semiconductors and facing the first electrodes, and pixel electrodes connected to the second electrodes.
1. A thin film transistor array panel comprising:
a substrate;
gate lines formed on the substrate;
polycrystalline semiconductors formed on the gate lines;
assistant layers formed on the polycrystalline semiconductors and including an amorphous semiconductor;
data lines formed on the polycrystalline semiconductors and including first electrodes;
second electrodes facing the first electrodes on the polycrystalline semiconductors; and
pixel electrodes connected to the second electrodes,
wherein the assistant layers have the same plan shape as the polycrystalline semiconductors.
2. The thin film transistor array panel of claim 1 , further comprising ohmic contacts between the polycrystalline semiconductors and the first and second electrodes.
3. The thin film transistor array panel of claim 2 , wherein the ohmic contact is an amorphous semiconductor doped with an impurity.
4. The thin film transistor array panel of claim 2 , wherein the ohmic contact is a polycrystalline semiconductor doped with an impurity.
5. A thin film transistor array panel comprising:
a substrate;
gate lines formed on the substrate and including gate electrodes;
data lines insulated from the gate lines and crossing the gate lines;
first electrodes connected to the data lines;
second electrodes facing the first electrodes;
pixel electrodes connected to the second electrodes;
a first semiconductor layer partially overlapping the first and second electrodes and including a polycrystalline semiconductor;
a second semiconductor layer formed on the first semiconductor layer and including an amorphous semiconductor; and
ohmic contacts formed between the second semiconductor layer and the first and second electrodes,
wherein the second semiconductor layer includes a first portion and a second portion having a smaller thickness than the first portion.
6. The thin film transistor array panel of claim 5 , wherein the second portion is located between the first electrode and the second electrode.