Granted Patent B2

US 7,531,888 · App. 11/564,948 · Granted May 12, 2009

Abstract

Claims (52)

1. A lateral insulated gate bipolar transistor (LIGBT) device, comprising:

a semiconductor substrate;

an anode region in said semiconductor substrate;

a cathode region of a first conductivity type in said substrate laterally spaced from said anode region;

a cathode region of a second conductivity type in said substrate located proximate to and on a side of said cathode region of said first conductivity type opposite from said anode region;

a drift region in said semiconductor substrate between said anode region and said cathode region of said first conductivity type;

an insulated gate operatively coupled to said cathode region of said first conductivity type located on a side of said cathode region of said first conductivity type opposite from said anode region; and

an insulating spacer overlying said cathode region of said second conductivity type;

wherein the lateral dimensions of said insulating spacer and said cathode region of said second conductivity type are substantially equal or substantially smaller than the lateral dimension of said cathode region of said first conductivity type.

2. The device of claim 1 wherein said first conductivity type is a p type and said second conductivity type is an n type.

3. The device of claim 1 wherein said lateral dimensions of said cathode region of said second conductivity type arc substantially smaller than the lateral dimension of said cathode of said first conductivity type.

4. The device of claim 1 wherein said anode region includes an anode of said first conductivity.

5. The device of claim 1 wherein said anode region includes interleaved segments of said first conductivity type and of said second conductivity type.

6. The device of claim 1 wherein said anode region includes a Schottky anode.

7. The device of claim 6 wherein said Schottky anode includes a silicide layer and a layer of one of first and second conductivity types.

8. The device of claim 1 wherein said drift region is a super junction drift region.

9. The device of claim 8 wherein said super junction drift region is one of a single JFET (Junction Field Effect Transistor), two stacked JFETs, or multiple JFETs.

10. The device of claim 8 wherein said super junction drift region includes first and second layers of a first conductivity type, a third layer intermediate said first and second layers, said third layer including alternating, interleaved pillars of said first conductivity type and of said second conductivity type extending between said anode and cathode regions.

11. The device of claim 8 wherein said super junction drift region includes first, second, and third layers of a first conductivity type, a fourth layer intermediate said first and second layers, said fourth layer including alternating, interleaved pillars of said first conductivity type and of a second conductivity type extending between said anode and said cathode regions; and wherein said drift region includes a fifth layer intermediate said second and third layers, said fifth layer including alternating, interleaved pillars of said first conductivity type and of a second conductivity type extending between said anode and said cathode regions.

12. A lateral insulated gate bipolar transistor (LIGBT) device, comprising:

a p substrate;

an n region formed on said p substrate;

a p body region formed in said n region;

an anode region;

a p+ cathode region formed in said p body region laterally spaced from said anode region;

an n+ cathode region formed in said p body region located proximate to and on a side of said p+ cathode region opposite from said anode region;

a conductive layer formed on said p+ cathode region and coupled to said n+ cathode region;

a drift region formed on said p substrate between said anode region and said p+ cathode region;

an insulated gate operatively coupled to said p+ cathode region located on a side of said p+ cathode region opposite from said anode region; and

an insulating spacer overlying said n+ cathode region;

wherein the lateral dimensions of said insulating spacer and said n+ cathode region are substantially equal or substantially smaller than the lateral dimension of said p+ cathode region.

13. The device of claim 12 wherein said anode region includes an p anode.

14. The device of claim 12 wherein said anode region includes interleaved p and n segments.

15. The device of claim 12 wherein said anode region includes a Schottky anode.

16. The device of claim 15 wherein said Schottky anode includes a silicide layer and an n layer.

17. The device of claim 12 wherein said drift region is a super junction drift region.

18. The device of claim 17 wherein said super junction drift region is one of a single JFET (Junction Field Effect Transistor), two stacked JFETs, or multiple JFETs.

19. The device of claim 17 wherein said super junction drift region includes first and second layers of a first conductivity type, a third layer intermediate said first and second layers, said third later including alternating, interleaved pillars of said first conductivity type and of said second conductivity type extending between said anode and cathode regions.

20. The device of claim 17 wherein said super junction drift region includes first, second, and third layers of a first conductivity type, a fourth layer intermediate said first and second layers, said fourth layer including alternating, interleaved pillars of said first conductivity type and of a second conductivity type extending between said anode and said cathode regions; and wherein said drift region includes a fifth layer intermediate said second and third layers, said fifth layer including alternating, interleaved pillars of said first conductivity type and of a second conductivity type extending between said anode and said cathode regions.

21. The device of claim 1 wherein said device has a deep trench isolation design.

22. The device of claim 1 wherein said device includes a RESURF drift region design.

23. The device of claim 1 wherein said device includes a buried p well region design.

24. The device of claim 12 wherein said device has a deep trench isolation design.

25. The device of claim 12 wherein said device includes a RESURF drift region design.

26. The device of claim 12 wherein said device includes a buried p well region design.

27. A process for making a lateral insulated gate bipolar transistor (LIGBT) device comprising the steps of:

forming an anode region in an active region of a semiconductor substrate;

forming a cathode region of a first conductivity type in said active region laterally spaced from said anode region;

forming a cathode region of a second conductivity type in said active region located proximate to and on a side of said cathode region of said first conductivity type opposite from said anode region;

forming a drift region in said active region between said anode region and said cathode region of said first conductivity type;

forming an insulated gate operatively coupled to said cathode region of said first conductivity type and located on a side of said cathode region of said first conductivity type opposite from said anode region; and

forming an insulating spacer overlying said cathode region of said second conductivity type.

Assignments (7)