IP Library Granted Patent US 7,873,125
Granted Patent B2
US 7,873,125 · App. 11/565,567 · Granted Jan 18, 2011

Method and system for sliding window phase estimator for WCDMA automatic frequency correction

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Quick Facts
Patent No.
US 7,873,125
App. No.
11/565,567
Granted
Jan 18, 2011
Kind
B2
Abstract

Aspects of a method and system for a sliding window phase estimator for wideband code division multiple access (WCDMA) automatic frequency correction are presented. Aspects of the system may include one or more circuits that enable adjustment of a current demodulation frequency for receiving at least one subsequent symbol based on a computed weighted sum of a plurality of computed frequency error values. Each of the plurality of computed frequency error values may be derived from a current symbol, a corresponding previous symbol, and/or a previous frequency error value. The current symbol may include a current received symbol segment and one or more previously received symbol segments.

Claims (32)

1. A method for frequency control in a communication system, the method comprising:

performing by one or more processors and/or circuits:

adjusting a current demodulation frequency for receiving at least one subsequent symbol based on a computed weighted sum of a plurality of computed frequency error values wherein each of said plurality of computed frequency error values is derived from one or more of: a current symbol, a corresponding previous symbol, and a previous frequency error value, wherein said current symbol comprises a current received symbol segment and one or more previously received symbol segments.

2. The method according to claim 1 , comprising generating a current chip level signal as a result of demodulating a current received signal based on said current demodulation frequency.

3. The method according to claim 2 , comprising generating said current received symbol segment as a result of despreading said current chip level signal by a corresponding despreading code.

4. The method according to claim 3 , comprising selecting a number of chips for said corresponding despreading code based on at least one previous computed weighted sum.

5. The method according to claim 1 , wherein said current symbol comprises said current received symbol segment and a selected number of most recently received said one or more previously received symbol segments.

6. The method according to claim 5 , wherein said corresponding previous symbol comprises said a selected number of most recently received said one or more previously received symbol segments and a symbol segment received previous to a last of said selected number of most recently received said one or more previously received symbol segments.

7. The method according to claim 1 , comprising computing at least one of said plurality of computed frequency error values based on at least one current phase value and a corresponding at least one previous phase value.

8. The method according to claim 1 , comprising computing at least one of said plurality of computed frequency error values based on said current symbol and a complex conjugate of said corresponding previous symbol.

9. The method according to claim 1 , wherein said computed weighted sum is computed based on maximal ratio combining of said plurality of computed frequency error values.

10. The method according to claim 1 , wherein said computed weighted sum is computed based on an equal gain combining of said plurality of computed frequency error values.

11. The method according to claim 1 , comprising computing an adjustment value for said adjusting said current demodulation frequency based on said computed weighted sum.

12. A system for frequency control in a communication system, the system comprising:

one or more circuits that are operable to adjust a current demodulation frequency for receiving at least one subsequent symbol based on a computed weighted sum of a plurality of computed frequency error values wherein each of said plurality of computed frequency error values is derived from one or more of: a current symbol, a corresponding previous symbol, and a previous frequency error value, wherein said current symbol comprises a current received symbol segment and one or more previously received symbol segments.

13. The system according to claim 12 , wherein said one or more circuits are operable to generate a current chip level signal as a result of demodulating a current received signal based on said current demodulation frequency.

14. The system according to claim 13 , wherein said one or more circuits are operable to generate said current received symbol segment as a result of despreading said current chip level signal by a corresponding despreading code.

15. The system according to claim 14 , wherein said one or more circuits are operable to select a number of chips for said corresponding despreading code based on at least one previous computed weighted sum.

16. The system according to claim 12 , wherein said current symbol comprises said current received symbol segment and a selected number of most recently received said one or more previously received symbol segments.

17. The system according to claim 16 , wherein said corresponding previous symbol comprises said a selected number of most recently received said one or more previously received symbol segments and a symbol segment received previous to a last of said selected number of most recently received said one or more previously received symbol segments.

18. The system according to claim 12 , wherein said one or more circuits are operable to compute at least one of said plurality of computed frequency error values based on at least one current phase value and said corresponding at least one previous phase value.

19. The system according to claim 12 , wherein said one or more circuits are operable to compute at least one of said plurality of computed frequency error values based on said current symbol and a complex conjugate of said corresponding previous symbol.

20. The system according to claim 12 , wherein said computed weighted sum is computed based on maximal ratio combining of said plurality of computed frequency error values.

21. The system according to claim 12 , wherein said computed weighted sum is computed based on an equal gain combining of said plurality of computed frequency error values.

22. The system according to claim 12 , wherein said one or more circuits are operable to compute an adjustment value for said adjustment of said current demodulation frequency based on said computed weighted sum.

23. A computer readable medium having stored thereon, a computer program having at least one code section for frequency control in a communication system, the at least one code section being executable by a computer for causing the computer to perform steps comprising:

adjusting a current demodulation frequency for receiving at least one subsequent symbol based on said computed weighted sum of a plurality of computed frequency error values wherein each of said plurality of computed frequency error values is derived from one or more of: a current symbol, a corresponding previous symbol, and a previous frequency error value, wherein said current symbol comprises a current received symbol segment and one or more previously received symbol segments.

24. The computer readable medium according to claim 23 , wherein said at least one code section comprises code for generating said current received symbol segment as a result of despreading a current chip level signal by a corresponding despreading code.

25. The computer readable medium according to claim 24 , wherein said at least one code section comprises code for selecting a number of chips for said corresponding despreading code based on at least one previous computed weighted sum.

26. The computer readable medium according to claim 23 , wherein said at least one code section comprises code for computing at least one of said plurality of computed frequency error values based on said current symbol and a complex conjugate of said corresponding previous symbol.

27. The computer readable medium according to claim 23 , wherein said computed weighted sum is computed based on an equal gain combining of said plurality of computed frequency error values.

28. The computer readable medium according to claim 23 , wherein said at least one code section comprises code for computing an adjustment value for said adjusting said current demodulation frequency based on said computed weighted sum.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
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To: BROADCOM CORPORATION
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2007
From: CONROY, HENDRIK JOHANNES; BOCCUZZI, JOSEPH
To: BROADCOM CORPORATION
Reel/Frame 018794/0663 →