Method for reducing silicide defects by removing contaminants prior to drain/source activation
View Patent ↗By consuming a surface portion of polysilicon material or silicon material after implantation and prior to activation of dopants, contaminants may be efficiently removed, thereby significantly enhancing the process uniformity during a subsequent silicidation process. Hence, the defect rate during the silicidation process, for instance “missing silicide” defects, may be significantly reduced, thereby also enhancing the reliability of static RAM cells.
1. A method comprising:
forming doped areas in a silicon containing semiconductor region covered by a dielectric layer, wherein the doped areas define an interface between a first doped region and a second doped region in a continuous region of the silicon containing semiconductor region and wherein said silicon containing semiconductor region represents a polysilicon line connecting at least two field effect transistors of different conductivity types;
removing said dielectric layer;
forming a sacrificial liner on at least a portion of said silicon containing semiconductor region including said interface;
annealing said silicon containing semiconductor region to activate dopants;
removing said sacrificial liner; and
forming a metal silicide in said silicon containing semiconductor region after removal of said sacrificial liner.
2. The method of claim 1 , wherein forming said doped areas comprises implanting a dopant of a first conductivity type into a first portion of said silicon containing semiconductor region while covering a second portion thereof, and implanting a dopant of a second conductivity type in said second portion while covering said first portion.
3. The method of claim 1 , wherein forming a sacrificial liner comprises performing a layer formation process that consumes a surface portion of said silicon containing semiconductor region.
4. The method of claim 3 , wherein forming said sacrificial liner comprises performing an oxidation process.
5. The method of claim 4 , wherein said oxidation process is performed at a temperature of approximately 500° C. or less.
6. The method of claim 5 , wherein said oxidation process comprises a plasma oxidation process.
7. The method of claim 4 , wherein said oxidation process comprises a wet chemical oxidation.
8. The method of claim 4 , wherein said sacrificial layer is removed on the basis of a wet chemical etch process.
9. The method of claim 8 , wherein said wet-chemical etch process is based on hydrofluoric acid (HF).
10. The method of claim 1 , wherein said dielectric layer is comprised of silicon dioxide.
11. The method of claim 1 , wherein a thickness of said sacrificial liner is in the range of approximately 2 to 10 nanometers.
12. A method comprising:
forming a cap layer over a silicon containing region;
doping the silicon containing semiconductor region through the cap layer to form at least two doped regions, wherein an interface is defined between a first doped region and a second doped region in a continuous region of the silicon containing semiconductor region;
oxidizing a surface portion of said doped silicon containing semiconductor region in the presence of said capping layer to form a sacrificial liner;
removing said sacrificial liner; and
forming metal silicide in said silicon containing semiconductor region.
13. The method of claim 12 , further comprising annealing said silicon containing semiconductor region to activate dopants.
14. The method of claim 13 , wherein said annealing is performed prior to removing said sacrificial liner.
15. The method of claim 12 , wherein oxidizing said surface portion is performed at a temperature of approximately 500° C. or less.
16. The method of claim 12 , wherein oxidizing said surface portion consumes a thickness of said silicon containing semiconductor regions of approximately 1 to 10 nanometers.