Array type operation device
View Patent ↗An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.
1. An array calculation device comprising:
a processor array composed of a plurality of processor elements having been assigned with orders;
an instruction acquiring unit operable to acquire an instruction in each cycle;
a first unit operable to generate, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generate an instruction to the processor element of the first order in accordance with the operation control information and the instruction acquired by the instruction acquiring unit; and
a second unit operable to generate, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generate an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated by the second unit in each cycle and the instruction acquired by the instruction acquiring unit.
2. The array calculation device of claim 1 , wherein
the plurality of processor elements constituting the processor array are connected to each other by signal lines, and
with respect to each of the plurality of processor elements, a calculation result of a processor element is transferred to a processor element of a next order, in each cycle via a signal line.
3. The array calculation device of claim 1 further comprising
a basic control information generating unit operable to generate basic control information in each cycle, wherein
the operation control information for controlling the operation of the processor element of the first order is generated in accordance with the basic control information generated by the basic control information generating unit.
4. The array calculation device of claim 1 , wherein
each processor element includes a data acquiring unit operable to acquire a plurality of types of data,
the operation control information includes specification information that specifies a type of data to be used when each processor element executes an instruction, and
each processor element acquires and uses data of the type specified by the specification information when executing an instruction.
5. The array calculation device of claim 1 , wherein
the operation control information is information that specifies whether or not to execute the instruction acquired by the instruction acquiring unit, and
if the operation control information specifies to execute the instruction, the processor element executes the instruction, and if the operation control information specifies not to execute the instruction, a power supply to the processor element is inhibited.
6. An array calculation device comprising:
a processor array of a two dimensional array structure in which processor elements are arranged in M lines by N columns, wherein N pieces of processor elements in each line are connected by signal lines, and the processor elements are connected so that a calculation result of each processor element is transferred to a processor element of a next line;
a basic control information generating unit operable to generate basic control information in each cycle;
an instruction acquiring unit operable to acquire an instruction in each cycle;
a first unit operable to generate, in each cycle, operation control information for controlling an operation of a processor element of a first line, in accordance with the basic control information generated by the basic control information generating unit, and then generate an instruction to the first line in accordance with the operation control information and the instruction acquired by the instruction acquiring unit; and
a second unit operable to generate, in each cycle, operation control information for controlling an operation of each processor element of 2-M lines, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding line, and then generate an instruction to each processor element of 2-M lines, in accordance with the operation control information generated by the second unit in each cycle and the instruction acquired by the instruction acquiring unit, wherein
the N pieces of processor elements in each line of the processor array execute an instruction to the line.