Granted Patent B2

US 7,685,488 · App. 11/572,808 · Granted Mar 23, 2010

Abstract

Claims (33)

1. A boundary scan circuit arrangement for detecting logic level crossing in an integrated circuit, the boundary scan circuit arrangement comprising:

a logic level crossing detection circuit including a flip-flop having a reset input coupled to a reset signal having a value that varies as a function of an actual logic level of the integrated circuit, the flip-flop being reset from a “1” to a “0” value as a function of the reset signal; and

the logic level crossing detection circuit being adapted to indicate a logic level crossing condition of the integrated circuit as a function of a reset condition of the flip-flop;

wherein:

the logic level crossing detection circuit further includes:

another flip-flop having a reset input coupled to another reset signal that varies as a function of an actual logic level of the integrated circuit; and

wherein the reset signals provided to each flip-flop reset input are respectively provided, for a particular logic level to reset one of the flip-flops and not the other; and

the logic level crossing detection circuit is adapted to indicate the logic-level crossing condition of the integrated circuit as a function of the reset condition of both flip-flops.

2. The arrangement of claim 1 , wherein the logic level crossing circuit is adapted to indicate a logic level crossing condition of the integrated circuit when both of the flip-flops are reset.

3. The arrangement of claim 1 , wherein the reset signals provided to each flip flop are susceptible to change in response to a change in the actual logic level of the integrated circuit, and wherein both flip-flops are reset when the actual logic level of the integrated circuit changes.

4. A boundary scan circuit arrangement for detecting logic level crossing in an integrated circuit, the boundary-scan circuit arrangement comprising:

first and second flip-flops;

a loading circuit configured and arranged to selectively;

load the first and second flip-flop circuits with a value;

hold the value in the first and second flip-flops; and

pass an actual logic level of the integrated circuit to the flip-flops;

a first reset circuit configured and arranged to reset the first flip-flop in response to a first actual logic level of the integrated circuit;

a second reset circuit configured and arranged to reset the second flip-flop in response to a second actual logic level of the integrated circuit that is the inverse of the first actual logic level; and

an enable circuit coupled to the first and second reset circuits and configured and arranged to provide a signal to enable the first and second reset circuits to pass a reset signal to the flip-flops.

5. The arrangement of claim 4 , wherein the first and second reset circuits are respectively adapted to reset the first and second flip-flops in response to the actual logic level switching between the first and second logic levels during a time period when the enable circuit provides an enable signal to the reset circuits.

6. The arrangement of claim 4 , further comprising a clocking circuit configured and arranged to provide a clock signal to the flip-flops for shifting out values in the flip-flops.

7. The arrangement of claim 4 , further comprising a comparison circuit configured and arranged to compare the values in the flip-flops and to output a signal indicative of the comparison.

8. The arrangement of claim 7 , wherein the comparison circuit is configured and arranged to output a signal indicating a logic level crossing in response to the values in both flip-flops being equal after the enable circuit has provided the enable signal.

9. The arrangement of claim 4 , wherein the first and second reset circuits and the flip-flops are configured and arranged such that:

during a period when the enable signal is provided, only one of the flip-flops is reset when die actual logic level of the integrated circuit is constant; and

during a period when fee enable signal is provided, both of the flip-flops are reset when the actual logic level of the integrated circuit crosses between logic levels.

10. A method for detecting logic level crossing in an integrated circuit, the method comprising:

providing a reset signal to a flip-flop, the reset signal having a value that varies as a function of an actual logic level of the integrated circuit, the flip-flop being reset from a “1” to a “0” value as a function of the reset signal;

indicating a logic level crossing condition of the integrated circuit as a function of a reset condition of the flip-flop; and

providing another reset signal to another flip-flop as a function of an actual logic level of the integrated circuit;

wherein providing the reset signals to each flip-flop includes providing, for a particular logic level, reset signals that respectively reset one of the flip-flops and not the other; and

wherein indicating the logic level crossing condition of the integrated circuit as a function of the reset condition includes indicating the logic level crossing condition of the integrated circuit as a function of the reset condition of both flip-flops.

11. The method of claim 10 , wherein providing the reset signals to each flip-flop includes providing reset signals to both flip-flops when the actual logic level of the integrated circuit switches between logic levels and wherein indicating the logic level crossing condition of the integrated circuit as a function of the reset condition of both flip-flops includes indicating a logic level crossing when bother flip-flops are reset.

Assignments (11)