Self-aligned epitaxially grown bipolar transistor
The illumination system has a light source ( 1 ) with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the first and the second primary colors being distinct from each other. The illumination system has a facetted light-collimator ( 2 ) for collimating light emitted by the light emitters. The facetted lightcollimator is arranged along a longitudinal axis ( 25 ) of the illumination system. Light propagation in the facetted light-collimator is based on total internal reflection or on reflection at a reflective coating provided on the facets of the facetted light-collimator. The facetted light-collimator merges into a facetted light-reflector ( 3 ) at a side facing away from the light source. The illumination system further comprises a light-shaping diffuser ( 17 ). The illumination system emits light with a uniform spatial and spatio-angular color distribution.
1. A method for forming a self-aligned bipolar transistor over a silicon substrate having a well region of a first polarity type, the method comprising:
defining a bipolar active region and field region in the bipolar region using a first bipolar mask, the active transistor area having an isolation region separating a bipolar region and a CMOS region, wherein defining the bipolar active area includes,
etching the bipolar active region to a predetermined depth, and forming spacers in the bipolar active region after etching the bipolar active region to a predetermined depth;
depositing a silicon-germanium-type (SiGe-type) base layer of a second polarity type into the bipolar active region and the field area, and
forming inside spacers on the SiGe-type base layer within the bipolar active region;
forming an emitter region between the inside spacers in the bipolar active region, wherein forming the emitter region includes,
filling the emitter region with doped silicon of a first polarity type,
defining an extrinsic base region using a second bipolar mask, removing material in the SiGe-type base layer as a function of masking protection provided by the second bipolar mask,
implanting a collector region within the CMOS region; and defining at least one contact area for each of the extrinsic base region, the emitter region, and the collector region of the active transistor areas.
2. The method as recited in claim 1 , wherein the polarity of the first type is opposite the polarity of the second type.
3. The method as recited in claim 2 , wherein the polarity of the first type is N-type and the polarity of the second type is P-type.
4. The method as recited in claim 2 , wherein the polarity of the first type is P-type and the polarity of the second type is N-type.
5. On a silicon substrate having a well region of a first polarity type, the well region apportioned into active transistor areas, the active transistor area having a bipolar region and a CMOS region, a method for forming a self-aligned bipolar transistor, the method comprising:
defining a bipolar active region and field region in the bipolar region with a first bipolar mask, wherein defining the bipolar active area includes,
etching the bipolar active region to a first predetermined depth,
forming spacers in the bipolar active region,
depositing a silicon-germanium (SiGe-type) base layer of a second polarity type into the bipolar active region and the field area, and
forming a U-cup spacer on the SiGe-type base layer within the bipolar active region, wherein forming U-cup spacer includes,
depositing a thin nitride layer on the SiGe-type base layer,
depositing a thick oxide on top of the thin nitride layer,
planarizing the thick oxide layer, stopping on the thin nitride layer,
removing the nitride layer from the SiGe-type base layer, and
increasing the depth of the bipolar active region to a second predetermined depth;
forming an emitter region between the inside spacers in the bipolar active region, wherein defining the emitter region includes,
filling the emitter region with doped silicon of a first polarity type,
defining an extrinsic base region with a second bipolar mask, removing SiGe-type base layer from those areas not protected by the second bipolar mask,
implanting a collector region within the CMOS region; and
defining at least one contact area for the extrinsic base region, the emitter region, and the collector region of the active transistor areas.
6. The method as recited in claim 5 , further comprising, forming spacers in the bipolar active region after etching the bipolar active region to a predetermined depth.
7. The method as recited in claim 5 , wherein the polarity of the first type is opposite the polarity of the second type.
8. The method as recited in claim 6 , wherein the polarity of the first type is N-type and the polarity of the second type is P-type.
9. The method as recited in claim 5 , wherein the polarity of the first type is P-type and the polarity of the second type is N-type.