SONOS memory device with optimized shallow trench isolation
View Patent ↗Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising: —providing the substrate having the first semiconductor layer; —depositing the charge trapping layer; —depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and —creating a shallow trench isolation in between said at least two non-volatile memory cells.
1. Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area said non-volatile memory device comprising a cell stack including a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first oxide layer; the method comprising:
providing the substrate having the first semiconductor layer;
depositing the charge trapping layer;
depositing the electrically conductive layer;
creating a protective layer on sidewalls of at least the charge trapping layer comprising at least the first oxide layer;
patterning the cell stack to form at least two non-volatile memory cells; and
after at least deposition of the charge trapping layer and creation of the protective layer, creating a shallow trench isolation in between said at least two nonvolatile memory cells;
wherein the protective layer is arranged for preventing a local change of a thickness of the first insulating layer at or near the sidewalls during a further processing step.
2. Method of manufacturing a non-volatile memory device according to claim 1 on a semiconductor substrate in a memory area, wherein the protective layer is a nitrogen-enriched layer formed by a plasma-nitridation process or a nitrogen implantation process.
3. Method of manufacturing a non-volatile memory device according to claim 1 on a semiconductor substrate in a memory area, wherein the protective layer is a spacer formed by deposition of a thin silicon nitride layer and a subsequent spacer etch process.
4. Method of manufacturing a non-volatile memory device according to claim 3 on a semiconductor substrate in a memory area, wherein the spacer has a spacer thickness along the surface of the first semiconductor layer; said step of creating said shallow trench isolation comprises the formation of trenches in between said at least two non-volatile memory cells, the trenches comprising trench walls in said semiconductor substrate, and the method further comprises:
thermally oxidizing the trench walls to obtain a silicon dioxide liner on said trench walls, the silicon dioxide liner having a liner thickness along the surface of the first semiconductor layer, the thermal oxidation being carried out in such a way that the liner thickness substantially equals the spacer thickness.
5. Method of manufacturing a non-volatile memory device according to any one of the preceding claims on a semiconductor substrate in a memory area, wherein the semiconductor substrate further comprises a logic area, and the method further comprises:
forming components on said logic area, said memory cell meanwhile being protected by said protective layer.
6. Method of manufacturing a non-volatile memory device according to any one of the preceding claims on a semiconductor substrate in a memory area, wherein the method further comprises:
filling the trenches with a dielectric material;
planarizing the dielectric material;
depositing a connect layer;
patterning the connect layer to provide first conductive lines on the nonvolatile memory cells;
providing a metallization pattern and a passivation layer.
7. Method of manufacturing a non-volatile memory device according to claim 6 on a semiconductor substrate in a memory area, wherein said patterning of the connect layer also comprises providing second conductive lines on the components in the logic area.
8. Method of manufacturing a non-volatile memory device according to claim 1 on a semiconductor substrate in a memory area, wherein the charge trapping layer is an Oxide-Nitride-Oxide (ONO) stack including a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
9. A non-volatile memory device comprising:
a cell stack including a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer, the cell stack being patterned to form a trench between at least two non-volatile memory cells;
a protective layer on sidewalls of said cell stack;
a liner on walls of said trench;
a shallow trench isolation provided in said trench;
wherein the thickness of said protective layer is substantially equal to the thickness of the liner.
10. Semiconductor device comprising at least a non-volatile memory device according to claim 9 .
11. The Method of manufacturing a non-volatile memory device according to claim 8 , wherein the protective layer is created on sidewalls of the first silicon oxide layer, on sidewalls of the silicon nitride layer, and on sidewalls of the second silicon oxide layer.