IP Library Patent Application 11577308
Patent Application
App. No. 11/577,308

ALL N-TYPE TRANSISTOR HIGH-SIDE CURRENT MIRROR

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
11/577,308
Abstract

The present invention relates to an all n-type transistor current mirror for mirroring an input current to an output current. The current mirror comprises an input n-type transistor (T 4, QO, T 1 ) interposed between a positive supply plane (VCC) and an input node ( 104, 202, 310 ) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the input node ( 104, 202, 310 ). An output n-type transistor (T 3, Q 1, T 2 ) is interposed between the positive supply plane (VCC) and an output node ( 106, 204, 314 ) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the output node ( 106, 204, 314 ). A feedback circuit equals base-emitter voltages of the input (T 4, QO, T 1 ) and the output transistor (T 3, Q 1, T 2 ) in order to mirror the emitter current of the input transistor (T 4, QO, T 1 ) to the emitter current of the output transistor (T 3, Q 1, T 2 ). The all n-type transistor current mirror is highly advantageous by overcoming the shortcomings of technologies such as MOBI 3, GaAs, and InP of being unable to provide p-type transistors.

Claims (51)

1 - 15 . (canceled)

16 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out comprising:

an input node for receiving the input current I_in;

an output node for providing the output current I_out;

an input n-type transistor interposed between a positive supply plane and the input node with its collector being connected to the positive supply plane and its emitter being connected to the input node;

an output n-type transistor interposed between the positive supply plane and the output node with its collector being connected to the positive supply plane and its emitter being connected to the output node; and,

a feedback circuit interposed between the input node and the output node, the feedback circuit being in communication with a link connecting the base of the input transistor with the base of the high side transistor, the feedback circuit for maintaining base-emitter voltages of the input and the output transistor equal in order to mirror the emitter current of the input transistor to the emitter current of the output transistor.

17 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 16 wherein the feedback circuit comprises an operational amplifier.

18 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 16 wherein the output node has a predetermined impedance.

19 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 17 wherein the output node has a predetermined impedance.

20 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 3 wherein the feedback circuit is dimensioned such that a loop gain of the feedback circuit is sufficient for providing the predetermined impedance.

21 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 17 wherein the operational amplifier is connected such that its positive input is connected to the output node, its negative input is connected to the input node, and its output is in communication with the link connecting the base of the input transistor with the base of the high side transistor.

22 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 17 wherein the operational amplifier is connected such that its positive input is connected to the output node, its negative input is connected to the input node, and its output is in communication with a base of a n-type feedback transistor interposed between the emitter of the output transistor and the output node.

23 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 22 wherein the link connecting the base of the input transistor with the base of the high side transistor is connected to the positive supply plane.

24 . An n-type transistor current mirror for mirroring an input current I_in to an output current I_out as defined in claim 23 comprising:

an input resistor interposed between the emitter of the input transistor and the feedback amplifier; and,

an output resistor interposed between the emitter of the output transistor and the feedback amplifier.

25 . An storage medium having data stored therein, the data for when executed resulting in an integrated circuit design of a n-type transistor current mirror for mirroring an input current I_in to an output current I_out comprising:

an input node for receiving the input current I_in;

an output node for providing the output current I_out;

an input n-type transistor interposed between a positive supply plane and the input node with its collector being connected to the positive supply plane and its emitter being connected to the input node;

an output n-type transistor interposed between the positive supply plane and the output node with its collector being connected to the positive supply plane and its emitter being connected to the output node; and,

a feedback circuit interposed between the input node and the output node, the feedback circuit being in communication with a link connecting the base of the input transistor with the base of the high side transistor, the feedback circuit for maintaining base-emitter voltages of the input and the output transistor equal in order to mirror the emitter current of the input transistor to the emitter current of the output transistor.

26 . An method for mirroring an input current I_in to an output current I_out comprising:

providing an input node for receiving the input current I_in;

providing an output node for providing the output current I_out;

providing an input n-type transistor interposed between a positive supply plane and the input node with its collector being connected to the positive supply plane and its emitter being connected to the input node;

providing an output n-type transistor interposed between the positive supply plane and the output node with its collector being connected to the positive supply plane and its emitter being connected to the output node;

providing a feedback circuit interposed between the input node and the output node, the feedback circuit being in communication with a link connecting the base of the input transistor with the base of the high side transistor; and,

mirroring the emitter current of the input transistor to the emitter current of the output transistor by maintaining base-emitter voltages of the input and the output transistor equal using the feedback circuit.

27 . An current mirror for mirroring an input current I_in to an output current I_out comprising:

an input node for receiving the input current I_in;

an output node for providing the output current I_out;

an input resistor interposed between a positive supply plane and the input node;

an output resistor interposed between the positive supply plane and the output node; and,

a feedback circuit interposed between the input node and the output node, the feedback circuit for maintaining voltage drops across the input and the output resistors equal in order to mirror the input current to the output current.

28 . An current mirror for mirroring an input current I_in to an output current I_out as defined in claim 27 wherein the output node has a predetermined impedance.

29 . An current mirror for mirroring an input current I_in to an output current I_out as defined in claim 28 wherein the feedback circuit is dimensioned such that a loop gain of the feedback circuit is sufficient for providing the predetermined impedance.

30 . An storage medium having data stored therein, the data for when executed resulting in an integrated circuit design of a current mirror for mirroring an input current I_in to an output current I_out comprising:

an input node for receiving the input current I_in;

an output node for providing the output current I_out;

an input resistor interposed between a positive supply plane and the input node;

an output resistor interposed between the positive supply plane and the output node; and,

a feedback circuit interposed between the input node and the output node, the feedback circuit for maintaining voltage drops across the input and the output resistors equal in order to mirror the input current to the output current.

31 . A method for mirroring an input current I_in to an output current I_out comprising:

providing an input node for receiving the input current I_in;

providing an output node for providing the output current I_out;

providing an input resistor interposed between a positive supply plane and the input node;

providing an output resistor interposed between the positive supply plane and the output node;

providing a feedback circuit interposed between the input node and the output node; and,

mirroring the input current to the output current by maintaining voltage drops across the input and the output resistors equal using the feedback circuit.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2009
From: GRILLO, GIUSEPPE; SANDULEANU, MIHAI; BREKELMANS, HANS
To: NXP, B.V.
Reel/Frame 022930/0564 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2007
From: GRILLO, GIUSEPPE; SANDULEANU, MIHAI; BREKELMANS, HANS
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 019170/0993 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2007
From: GRILLO, GIUSEPPE; SANDULEANU, MIHAI; BREKELMANS, HANS
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 019170/0996 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2007
From: GRILLO, GIUSEPPE; SANDULEANU, MIHAI; BREKELMANS, HANS
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 019172/0001 →