Frequency offset cancellation circuit for data determination in wireless communications
View Patent ↗A demodulating semiconductor integrated circuit device used in a wireless communication system of an FM-modulation scheme, wherein a circuit for canceling a frequency offset is made of a digital circuit, so as to make a high-accuracy decision as to received data and prevent error frequency offset cancel due to a pseudo pattern contained in the received data. Consequently, a high-accuracy received data decision is carried out.
1. A system for wireless communication complying with a communication scheme defined to carry out data transmission with a predetermined pattern being added to a head of to be transmitted data, and including a semiconductor integrated circuit device,
the semiconductor integrated circuit device comprising:
a first conversion means for converting a receive signal, which is an analog signal including the predetermined pattern added in front of transmitted data, into a digital signal;
a demodulation means for demodulating the digital signal and outputting a demodulated data;
a detection means for receiving the demodulated data, recognizing the predetermined pattern added in front of the transmitted data, and generating a determination level signal , said detection means being made up of a digital circuit; and
a determination means for determining the demodulated data based on the determination level signal,
wherein the determination level signal instructs a threshold level of high data or low data for determining the demodulated data, so that the semiconductor integrated circuit device cancels a frequency offset from the receive signal.
2. A system for wireless communication according to claim 1 , wherein the detection means includes a first circuit which detects the predetermined pattern, a second circuit which detects a center level of the demodulated data, and a third circuit which generates the determination level signal and determines the demodulated data based on a signal detected by the first circuit and a center level detected by the second circuit.
3. A system for wireless communication according to claim 2 , wherein the second circuit detects levels of intersection points of the demodulated data and data obtained by delaying the demodulated data by one symbol period, and outputs an average value of the detected intersection-point levels as the center level.
4. A system for wireless communication according to claim 2 , wherein the first circuit includes a pattern recognition circuit which recognizes the predetermined pattern contained in the demodulated data, a level detection circuit which detects an average level of the demodulated data, and an operation circuit which receives outputs of the pattern recognition circuit and the level detection circuit and generates a predetermined pattern detect signal.
5. A system for wireless communication according to claim 2 , wherein the third circuit sets a value obtained by adding a predetermined value to the center level received from the second circuit as a first initial value, sets a value obtained by subtracting a predetermined value from the center level as a second initial value, averages the first initial value and the demodulated data with respect to a received-data level increasing direction to obtain a first average value, averages the second initial value and the demodulated data with respect to a received-data level decreasing direction to obtain a second average value, and outputs a value obtained by averaging the first and second average values as a determination level.
6. A system for wireless communication according to claim 1 , further comprising
a transmitting/receiving antenna;
transmit-receive selecting means for switching to connections between the antenna and a reception-system, said reception-system including the first conversion means, the demodulation means, the detection means, and a determination means or a transmission-system circuit which is formed on the semiconductor integrated circuit device; and
a baseband circuit which generates data delivered to the transmission-system circuit and processes data received from the reception-system circuit.