Method for manufacturing thin film transistor

1. A method for manufacturing a thin film transistor (TFT), the TFT comprising a source electrode, a drain electrode, and a groove between the source electrode and the drain electrode, the method comprising:

providing an insulating substrate, and coating a gate metal layer on the insulating substrate;

forming a gate electrode from the gate metal layer;

coating a gate insulation layer, an amorphous silicon (a-Si) layer, an impurity-doped a-Si layer, and a source/drain electrode metal layer in that order on the gate electrode;

providing a photomask having at least one slit configuration;

forming a source/drain electrode metal pattern;

forming an a-Si layer pattern and an impurity-doped a-Si layer pattern; and

forming a source electrode; a drain electrode, and a groove;

wherein the at least one slit configuration of the photomask has a transmission region corresponding to the groove, and at least two opaque regions respectively corresponding to the source electrode and the drain electrode, the transmission region having at least one turning region and at least one other region, and the at least one turning region has a narrower width than that of the at least one other region.

2. The method as claimed in claim 1 , further comprising forming a passivation layer on the source electrode, the drain electrode and the groove.

3. The method as claimed in claim 1 , wherein the at least one slit has a generally U-shaped configuration.

4. The method as claimed in claim 1 , wherein the at least one slit defines a plurality of turning regions.

5. The method as claimed in claim 4 , wherein the at least one turning region has an angular configuration or a curved configuration.