Thin film transistor having openings formed therein
View Patent ↗A thin film transistor array panel includes a substrate, a plurality of first and second signal lines crossing each other on the substrate, source electrodes connected to the first signal lines, drain electrodes connected to the second signal lines, pixel electrodes connected to the drain electrodes, a first partition formed on the source and drain electrodes and having a first opening, wherein a lower width of the first opening is wider than an upper width of the first opening, an organic semiconductor formed in the first opening and at least overlapping the portions of the source electrode and the drain electrode, and a gate electrode connected to the second signal line and at least overlapping the portion of the organic semiconductor.
1. A thin film transistor array panel comprising:
a substrate;
a plurality of first and second signal lines crossing each other on the substrate;
source electrodes connected to the first signal lines;
drain electrodes connected to the second signal lines;
pixel electrodes connected to the drain electrodes;
a first partition formed on the source and the drain electrodes and having a first opening, wherein a lower width of the first opening is wider than an upper width of the first opening;
semiconductor formed in the first opening, wherein the semiconductor contacts side portion of the first partition and at least overlaps the portions of the source electrode and the drain electrode; and
a gate electrode connected to the second signal line and at least overlapping the portion of the semiconductor.
2. The thin film transistor array panel of claim 1 , wherein the first partition has an inverse tapered structure.
3. The thin film transistor array panel of claim 2 , wherein the first partition includes a negative photoresist material.
4. The thin film transistor array panel of claim 2 , further comprising a gate insulator formed between the gate electrode and the semiconductor, and including an organic material.
5. The thin film transistor array panel of claim 4 , wherein the gate insulator is enclosed by the first partition.
6. The thin film transistor array panel of claim 4 , further comprising a blocking member formed under the gate electrode.
7. The thin film transistor array panel of claim 1 , wherein the source electrode and the drain electrode include ITO or IZO.
8. The thin film transistor array panel of claim 1 , further comprising a storage electrode formed with the same layer as the first signal line and overlapping the pixel electrode.
9. The thin film transistor array panel of claim 1 , further comprising a light blocking layer formed under the semiconductor.
10. The thin film transistor array panel of claim 1 , further comprising a passivation member covering the gate electrode.
11. The thin film transistor array panel of claim 2 , further comprising a second partition formed under the first partition and including a second opening, and wherein the lower width of the second opening is wider than the upper width of the second opening.
12. The thin film transistor array panel of claim 11 , wherein the second opening is larger than the first opening.
13. The thin film transistor array panel of claim 11 , further comprising a gate insulator formed in the second opening.
14. The thin film transistor array panel of claim 13 , wherein the second opening has an inverse tapered structure.