Lead frame having outer leads coated with a four layer plating
View Patent ↗A lead frame base is coated with a four-layer plating. The four-layer plating includes an underlayer plating (Ni), a palladium plating, a silver plating and a gold plating arranged in this order from bottom to top.
1. A lead frame comprising a die pad for mounting a semiconductor element thereon, inner leads electrically connected to electrode pads of the semiconductor element and outer leads connected to the inner leads to function as external terminals, wherein
at least both the ends of the respective inner leads and the ends of the respective outer leads opposite to the inner leads are coated with a four-layer plating,
first three layers in the four-layer plating from the topmost surface thereof are made of Au, Ag and Pd, respectively,
a Au layer made of Au is the topmost layer, and a Ag layer made of Ag is formed between the layer made of Au and a Pd layer made of Pd, and
the Ag layer is not less than 0.05 μm and not more than 0.5 μm in thickness.
2. The lead frame of claim 1 , wherein
the outer leads are arranged at a pitch of not less than 300 μm and not more than 500 μm.
3. The lead frame of claim 1 , wherein
each of the outer leads is not less than 80 μm and not more than 250 μm in width.
4. The lead frame of claim 1 , wherein
the Pd layer in the four-layer plating is not less than 0.005 μm and not more than 0.2 μm in thickness.
5. The lead frame of claim 1 , wherein
the Au layer in the four-layer plating is not less than 0.0015 μm and not more than 0.1 μm in thickness.
6. The lead frame of claim 1 , wherein
the lead frame is made of Cu or Fe.
7. The lead frame of claim 1 , wherein
the four-layer plating consists of the Au layer as the topmost layer, the Ag layer, the Pd layer and a Ni layer as an undermost layer.
8. The lead frame of claim 7 , wherein
the Ni layer in the four-layer plating is not less than 0.2 μm and not more than 3.0 μm in thickness.
9. The lead frame of claim 1 , wherein the Ag layer is not less than 0.1 μm and not more than 0.5 μm in thickness.
10. The lead frame of claim 9 , wherein the entirety of the inner leads and the outer leads are coated with the four-layer plating.
11. A semiconductor device comprising:
the lead frame according to claim 9 ;
the semiconductor element mounted on the lead frame; and
connecting members electrically connect the inner leads to electrode pads on the semiconductor element,
wherein adjacent layers in the four-layer plating are alloyed with each other.
12. The lead frame of claim 1 , wherein the entirety of the inner leads and the outer leads are coated with the four-layer plating.
13. A semiconductor device comprising:
the lead frame according to claim 1 ;
the semiconductor element mounted on the lead frame; and
connecting members electrically connect the inner leads to electrode pads on the semiconductor element,
wherein adjacent layers in the four-layer plating are alloyed with each other.