IP Library Granted Patent US 7,486,133
Granted Patent B2
US 7,486,133 · App. 11/584,319 · Granted Feb 3, 2009

Transmitting output stage with adjustable output power and process for amplifying a signal in a transmitting output stage

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Quick Facts
Patent No.
US 7,486,133
App. No.
11/584,319
Granted
Feb 3, 2009
Kind
B2
Abstract

In one embodiment of a transmitting output stage, a first controllable amplification device with a first amplification factor and a second amplification device with a second amplification factor are provided. The two amplification devices are connected on the input side to a signal input. The transmitting output stage comprises a first matching network, which is connected on the input side to an output of first amplification device. A second matching network is also provided, which is installed switchably between an output of the second amplifier stage and the input of the first matching network and which, in one operating mode of the transmitting output stage in which only the second amplifier stage is being used, is connected between the second amplifier stage and the first matching network. Other embodiments are also disclosed.

Claims (55)

1. A transmitting output stage with adjustable amplification, comprising:

a signal input;

a first controllable amplification device having a first amplification factor, wherein the first controllable amplification device has an input side connected to the signal input;

a second amplification device having a second amplification factor, wherein the second amplification device has an input side connected to the signal input;

a first matching network having an input side connected to an output of the first controllable amplification device;

a second matching network having an input side connected to an output of the second amplification device and having an output side connected to a node between the first amplification device and the first matching network, the second matching network having at least one matching element and a device for selectively changing the impedance of at least the one matching element;

where the second matching network comprises an inductive element and a series-connected capacitative element, where a node between the inductive element and the capacitative element is connected to the output of the second amplification device.

2. The transmitting output stage according to claim 1 , where the device is configured so that the one matching element can selectively be bridged or deactivated.

3. The transmitting output stage according to claim 1 , where the first controllable amplification device is configured to provide a high maximum output power level, and the second amplification device is configured to provide a low maximum output power level.

4. The transmitting output stage according to claim 1 , where the first controllable amplification device is configured to provide a low maximum output power level, and the second amplification device is configured to provide a high maximum output power level.

5. The transmitting output stage according to claim 1 , where the first controllable amplification device is designed with a high amplification factor, and the second amplification device is designed with a low amplification factor.

6. The transmitting output stage according to claim 1 , where the first controllable amplification device comprises a control input, to which a control signal for deactivating the first controllable amplification device can be sent.

7. The transmitting output stage according to claim 6 , where the control signal is used to set a working point of the first controllable amplification device.

8. The transmitting output stage according to claim 2 , wherein the device for selectively bridging or deactivating further comprises a switch installed in a signal path parallel to the second matching network, where the switch facilitates the selective bridging or deactivating.

9. The transmitting output stage according to claim 1 , where the device comprises: a transistor that is coupled between a reference potential terminal and the second matching network; where the transistor having a base terminal to which a switching signal for bridging the second matching network can be sent.

10. The transmitting output stage according to claim 1 , where the second matching network is configured to transform a low impedance to a high impedance.

11. The transmitting output stage according to claim 1 , where the first controllable amplification device and the second amplification device each comprise at least one amplification transistor, the amplification transistors having different geometric parameters that relate to a ratio that corresponds to the ratio between the first amplification factor and the second amplification factor.

12. The transmitting output stage according to claim 1 , where the first controllable amplification device, the second amplification device, and the second matching network are implemented as an integrated circuit in a semiconductor body, and the first matching network is connected to a contact point on the surface of the semiconductor body.

13. A transmitting output stage with adjustable amplification, comprising:

a signal input;

a first amplifier stage having a first maximum output power;

a second amplifier stage in parallel with the first amplifier stage, where the second amplifier stage has a second maximum output power that is different from the first maximum output power;

a first matching network configured to match impedance to a load impedance during operation with the first and second amplifier stages, the first matching network having an input connected to the first amplifier stage;

a second matching network that is switchably installed between an output of the second amplifier stage and the input of the first matching network, and where the second matching network is connected between the second amplifier stage and the first matching network during an operating mode of the transmitting output stage in which the second amplifier stage is being used while the first amplifier stage is deactivated;

where in an operating mode of the transmitting output stage in which both the first and the second amplifier stages are being used, the first matching network is connected to the output of the second amplifier stage.

14. The transmitting output stage according to claim 13 , where the first matching network is designed for matching to a low load impedance, and the second matching network is designed for matching to a high load impedance.

15. The transmitting output stage according to claim 13 , where the first matching network is designed for matching to a high load impedance, and the second matching network is designed for matching to a low load impedance.

16. The transmitting output stage according to claim 13 , where the transmitting output stage comprises a control input, to which a control signal can be sent to select a first operating mode or a second operating mode, the control input being connected to the first amplifier stage and to the second matching network.

17. The transmitting output stage according to claim 13 , in which the first amplifier stage has a high amplification factor, and the second amplifier stage has a low amplification factor.

18. The transmitting output stage according to claim 13 , where the second matching network, in the second operating mode of the transmitting output stage, is designed for transformation of a low impedance to a high impedance.

19. A process for amplifying a signal in a transmitting output stage, comprising:

preparing a signal;

selecting an amplification setting;

selecting an impedance matching as a function of the selected amplification setting;

amplifying the signal by the selected amplification factor;

changing the amplification setting;

changing the impedance matching by bridging elements responsible for the impedance matching;

where changing the impedance matching comprises at least one of the following:

transforming a low impedance to a high impedance when the amplification setting is adjusted to a value below a limit value;

transforming a high impedance to a low impedance when the amplification setting is adjusted to a value above a limit value.

20. The process according to claim 19 , where the selection of an amplification setting comprises:

providing a first amplifier stage with a first amplification factor;

providing an amplifier stage with a second amplification factor;

selecting the first and the second amplifier stages or selecting the second amplifier stage for signal amplification.

21. A process for amplifying a signal in a transmitting output stage, comprising:

preparing a signal;

selecting an amplification setting;

selecting an impedance matching as a function of the selected amplification setting;

amplifying the signal by the selected amplification factor;

changing the amplification setting;

changing the impedance matching by bridging elements responsible for the impedance matching;

where the selection of an amplification setting comprises:

providing a first amplifier stage with a first amplification factor;

providing an amplifier stage with a second amplification factor;

selecting both the first and the second amplifier stages at a first time for signal amplification, and selecting only one of the first or second amplifier stages at a second time for signal amplification.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053518/0586 →
CONFIRMATORY ASSIGNMENT EFFECTIVE AS OF JANUARY 1, 2018 Recorded Aug 12, 2020
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 053477/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2007
From: BAKALSKI, WINFRIED DR.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018774/0072 →