IP Library Granted Patent US 7,675,310
Granted Patent B2
US 7,675,310 · App. 11/584,840 · Granted Mar 9, 2010

Device under test power supply

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Quick Facts
Patent No.
US 7,675,310
App. No.
11/584,840
Granted
Mar 9, 2010
Kind
B2
Abstract

A power supply includes a first amplifier, a first current stage, and a second current stage. The first amplifier is configured to set an output voltage equal to a fixed input voltage for supplying to a device. The first current stage is configured to source and sink a first range of first output currents and provide a first measurement current representing a first output current. The second current stage is configured to source and sink a second range of second output currents and provide a second measurement current representing a second output current in response to the first range being exceeded. The first output current and the second output current are summed for supplying to the device. The first measurement current and the second measurement current are summed at a node.

Claims (59)

1. A power supply comprising:

a first amplifier configured to set an output voltage equal to a fixed input voltage for supplying to a device;

a first current stage configured to source and sink a first range of first output currents and provide a first measurement current representing a first output current; and

a second current stage configured to source and sink a second range of second output currents and provide a second measurement current representing a second output current in response to the first range being exceeded,

wherein the first output current and the second output current are summed for supplying to the device, and

wherein the first measurement current and the second measurement current are summed at a node.

2. The power supply of claim 1 , further comprising:

a first range offset stage configured to enable the second current stage in response to the first range being exceeded.

3. The power supply of claim 2 , wherein the first range offset stage comprises:

a first range offset for offsetting a first signal for enabling a sourcing portion of the second current stage; and

a second range offset for offsetting a second signal for enabling a sinking portion of the second current stage.

4. The power supply of claim 3 , wherein the first range offset comprises a first transistor configured as a first source follower and wherein the second range offset comprises a second transistor configured as a second source follower.

5. The power supply of claim 1 , further comprising:

a circuit configured to measure a current at the node.

6. The power supply of claim 5 , wherein the circuit comprises:

at least two switches, each switch coupled to the node; and

at least two resistors, each resistor coupled to a switch,

wherein one of the switches is closed to select one of the resistors for determining the current at the node based on a voltage across the selected resistor.

7. The power supply of claim 6 , wherein the circuit comprises:

a second amplifier configured to set a voltage of the node equal to the output voltage.

8. The power supply of claim 1 , further comprising:

a third current stage configured to source and sink a third range of third output currents and provide a third measurement current representing a third output current in response to the second range being exceeded,

wherein the first output current, the second output current, and the third output current are summed for supplying to the device, and

wherein the first measurement current, the second measurement current, and the third measurement current are summed at the node.

9. The power supply of claim 8 , further comprising:

a second range offset stage configured to enable the third current stage in response to the second range being exceeded.

10. The power supply of claim 1 , wherein the first current stage composes:

a first voltage controlled current source configured to source the first range of first output currents; and

a second voltage controlled current source configured to sink the first range of first output currents.

11. The power supply of claim 10 , wherein the first voltage controlled current source comprises:

a first current source configured to provide the first output current; and

a second current source configured to provide the first measurement current.

12. The power supply of claim 11 , wherein the first current source comprises a first transistor and wherein the second current source comprises a second transistor.

13. A power supply comprising:

means for setting an output voltage equal to a fixed input voltage for supplying to a device under test;

means for sourcing and sinking a first range of first output currents and providing a first measurement current representing a first output current;

means for sourcing and sinking a second range of second output currents and providing a second measurement current representing a second output current in response to the first range being exceeded;

means for summing the first output current and the second output current for supplying to the device under test; and

means for summing the first measurement current and the second measurement current to provide a summed measurement current.

14. The power supply of claim 13 , further comprising:

means for measuring the summed measurement current.

15. The power supply of claim 14 , wherein the means for measuring the summed measurement current comprises means for setting a voltage equal to the output voltage at the means for summing the first measurement current and the second measurement current.

16. The power supply of claim 13 , further comprising:

means for sourcing and sinking a third range of third output currents and providing a third measurement current representing a third output current in response to the second range being exceeded;

means for summing the first output current, the second output current, and the third output current for supplying to the device under test; and

means for summing the first measurement current, the second measurement current, and the third measurement current to provide the summed measurement current.

17. A method for supplying power to a device, the method comprising:

setting an output voltage equal to a fixed input voltage for supplying to the device;

sourcing and sinking a first range of first output currents and providing a first measurement current representing a first output current;

sourcing and sinking a second range of second output currents and providing a second measurement current representing a second output current in response to the first range being exceeded;

summing the first output current and the second output current for supplying to the device; and

summing the first measurement current and the second measurement current to provide a summed measurement current.

18. The method of claim 17 , further comprising:

measuring the summed measurement current.

19. The method of claim 18 , wherein measuring the summed measurement current comprises setting a voltage equal to the output voltage where the first measurement current and the second measurement current are summed.

20. The method of claim 17 , further comprising:

sourcing and sinking a third range of third output currents and providing a third measurement current representing a third output current in response to the second range being exceeded;

summing the first output current, the second output current, and the third output current for supplying to the device; and

summing the first measurement current, the second measurement current, and the third measurement current to provide the summed measurement current.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Jul 25, 2019
From: CALIFORNIA MEZZANINE INVESTMENT FUND, L.P.
To: ELEVATE SEMICONDUCTOR, INC.
Reel/Frame 049865/0303 →
SECURITY INTEREST Recorded Jul 17, 2019
From: ELEVATE SEMICONDUCTOR, INC.
To: EAST WEST BANK
Reel/Frame 049781/0414 →
RELEASE OF SECURITY INTEREST Recorded Jun 28, 2019
From: AVIDBANK
To: ELEVATE SEMICONDUCTOR, INC.
Reel/Frame 049624/0036 →
SECURITY INTEREST Recorded Dec 12, 2018
From: ELEVATE SEMICONDUCTOR, INC.
To: AVIDBANK
Reel/Frame 047759/0909 →
SECURITY INTEREST Recorded Aug 31, 2018
From: ELEVATE SEMICONDUCTOR, INC.
To: CALIFORNIA MEZZANINE INVESTMENT FUND, L.P.
Reel/Frame 046770/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2015
From: INTERSIL AMERICAS LLC
To: ELEVATE SEMICONDUCTOR, INC.
Reel/Frame 035770/0045 →
RELEASE OF SECURITY INTEREST Recorded Jan 14, 2015
From: MORGAN STANLEY & CO. L.L.C.
To: INTERSIL AMERICAS INC.
Reel/Frame 034714/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2014
From: PLANET ATE LLC
To: INTERSIL AMERICAS LLC
Reel/Frame 034149/0284 →
CHANGE OF NAME Recorded Nov 11, 2014
From: PLANET ATE, INC.
To: PLANET ATE LLC
Reel/Frame 034204/0687 →
SECURITY AGREEMENT Recorded May 5, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.; ZILKER LABS, INC.; KENET, INC.; INTERSIL AMERICAS INC.; ELANTEC SEMICONDUCTOR, INC.; D2AUDIO CORPORATION; PLANET ATE, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024337/0395 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2006
From: SULLIVAN, PATRICK GERARD
To: PLANET ATE, INC.
Reel/Frame 018459/0674 →