Systems and methods for interconnect metallization using a stop-etch layer

1. A method for performing a single lithography step interconnect metallization using a stop-etch layer comprising:

depositing a stop-etch layer over the entire surface of a semiconductor device;

depositing an interconnect metallization material over the stop-etch layer;

performing a single lithography step to pattern a mask over the interconnect metallization material;

etching the interconnect metallization material in non-masked areas to form a hole through the interconnect metallization material, where the etching is blocked by the stop-etch layer; and

partially removing the stop-etch layer from said semiconductor device.

2. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where the stop-etch layer is a chrome layer.

3. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 2 , where depositing the stop-etch layer includes evaporating chrome over the wafer.

4. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where the interconnect metallization material has a first coefficient of thermal expansion that closely matches a second coefficient of thermal expansion of a semiconductor material underlying the semiconductor device.

5. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 4 , where the semiconductor material is selected from the group consisting of silicon carbide and gallium nitride.

6. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where the stop-etch layer material has a third coefficient of thermal expansion that closely matches a second coefficient of thermal expansion of a semiconductor material underlying the semiconductor device.

7. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 6 , where the semiconductor material is selected from the group consisting of silicon carbide and gallium nitride.

8. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where the interconnect metallization material is tungsten.

9. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 8 , where the tungsten is chemical-vapor-deposited over the stop-etch layer.

10. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where the interconnect metallization material is a mixture of titanium, nitrogen, and tungsten.

11. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 10 , where the mixture of titanium, nitrogen, and tungsten is sputtered over the stop-etch layer.

12. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where etching the interconnect metallization material comprises using a reactive-ion-etching process.

13. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where etching the interconnect metallization material comprises using a wet chemical etching process.

14. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where etching the interconnect metallization material comprises using a dry chemical etching process.

15. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , further comprising over etching the interconnect metallization material for a time sufficient to assure uniformity across a wafer.

16. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , further comprising over etching the interconnect metallization material for a time sufficient to assure uniformity across a die.

17. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where removing the stop-etch layer comprises performing a chemical dip.

18. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where removing the stop-etch layer comprises exposing the semiconductor device to a radio frequency (RF) process.

19. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where the semiconductor device is a power device.

20. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , wherein the semiconductor device is a radio frequency (RF) device.

21. A method for performing a single lithography step interconnect metallization using a stop-etch layer, comprising:

depositing the stop-etch layer over the entire surface of a wafer;

depositing an interconnect metallization layer over the stop-etch layer;

performing a mask over the interconnect metallization layer;

etching the interconnect metallization layer to form a hole through the interconnect metallization layer, where the etching stops at the stop-etch layer; and

partially removing the stop-etch layer from the wafer.

22. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 21 , where the stop-etch layer comprises a chrome layer.

23. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 21 , where the interconnect metallization layer comprises a material selected from the group consisting of tungsten and molybdenum.

24. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 21 , where the mask is selected from the group consisting of: a dielectric mask, a resist mask, and a metal mask.

25. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 21 , where the wafer comprises a semiconductor material selected from the group consisting of silicon carbide and gallium nitride.

26. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 21 , further comprising over etching the interconnect metallization layer for a time sufficient to assure uniformity across the wafer.

27. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 1 , where the mask is selected from the group consisting of: a dielectric mask, a resist mask, and a metal mask.

28. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 27 , where the mask is a metal mask and said metal mask remains as part of the semiconductor device once patterned over the interconnect metallization material.

29. The method for performing a single lithography step interconnect metallization using a stop-etch layer according to claim 24 , where the mask is a metal mask and said metal mask remains as part of the wafer once patterned over the interconnect metallization layer.