IP Library Patent Application 11586711
Patent Application
App. No. 11/586,711

Bus system for integrated circuit

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Quick Facts
Patent No.
US None
App. No.
11/586,711
Abstract

A bus system is disclosed for establishing signal connections to a plurality of functional units standing in operative connection to the integrated circuit, which are designed to generate and/or process digital and/or analog signals. The system includes a digital bus and an analog bus. The inclusion of an analog bus in an integrated circuit in addition to a digital bus has the result of complete modularity of the integrated circuit with regard to the use of a wide variety of functional units, so that the integrated circuit can be used in practically any way desired. In addition, because of the presence of an additional analog bus, the analog-to-digital and digital-to-analog converters normally present according to the prior art may be omitted, resulting in a corresponding saving of space and power.

Claims (16)

1 . A bus system internal to an integrated circuit for establishing signal connections to a plurality of functional units standing in operative connection to the integrated circuit, which generate and/or process digital and/or analog signals, the bus system comprising:

a digital bus; and

an analog bus.

2 . The bus system according to claim 1 , further comprising a central master control unit for the digital bus and for the analog bus, the control unit being designed for time-controlled delivery of digital signals and/or analog signals to the appropriate functional units.

3 . The bus system according to claim 1 , further comprising a plurality of interface functional modules, each of which is designed to connect at least one functional unit to the bus system ( 4 ).

4 . The bus system according to claim 3 , wherein the interface functional modules are IP modules.

5 . The bus system according to claim 3 , wherein the interface functional modules route digital signals received from the applicable functional units on the digital bus, and route analog signals received from the applicable functional units on the analog bus.

6 . The bus system according to claim 2 , wherein the master control unit stands in connection with at least one memory unit and/or data processing unit.

7 . The bus system according to claim 2 , wherein the master control unit is a state machine.

8 . The bus system according to claim 2 , wherein the master control unit is set up in software for signal transmission on the digital bus and on the analog bus.

9 . The bus system according to claim 2 , wherein the master control unit is set up for signal transmission on the digital bus and on the analog bus according to predefined assignments or in the form of ROM tables.

10 . The bus system according to claim 1 , further comprising an interface for connecting a test apparatus that is designed for testing at least one of the functional units, interface functional modules, or signal transmission configuration of the master control unit.

11 . An Integrated circuit for connecting a number of functional units, comprising the bus system according to claim 1 .

12 . A circuit arrangement comprising:

an integrated circuit according to claim 11 , and

a plurality of functional units connected to the integrated circuit, which generate and/or process digital and/or analog signals.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2009
From: ATMEL GERMANY GMBH
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 023205/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2006
From: FISCHER, HARALD
To: ATMEL GERMANY GMBH
Reel/Frame 018472/0673 →