Manufacturing method of high-voltage MOS transistor
In the manufacturing method of a high-voltage MOS, a structural body is prepared. The structural body includes a semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via a gate insulation film, and first conductive layers of a second conductivity type extending from the surface to the inside of the semiconductor substrate. Main sidewalls are formed on the first conductive layers, and contact whole side surfaces of the gate electrode. Side surfaces of the main sidewalls are perpendicular to the surface of the semiconductor substrate. At least one sub-sidewall is formed on at lest one first conductive layer, and contacts a whole side surface of the main sidewall. Impurities are doped into exposed regions of the first conductive layer through the mask using the gate electrode, the main sidewalls and the sub-sidewall, to thereby form heavily-doped impurity regions of the second conductivity type.
1 . A manufacturing method of a high-voltage MOS transistor comprising the steps of:
preparing a structural body including a semiconductor substrate of a first conductivity type, a gate electrode formed on a surface of said semiconductor substrate via a gate insulation film, and first conductive layers of a second conductivity type formed extending form said surface to inside of said semiconductor substrate, said first conductive layers being disposed on both sides of said gate electrode symmetrically to each other as said semiconductor substrate is seen from said surface side;
forming main sidewalls having electric conductivity respectively on said first conductive layers so that said main sidewalls contact whole side surfaces of said gate electrode, side surfaces of said main sidewalls opposite to said gate electrode being perpendicular to said surface of said semiconductor substrate;
forming at least one sub-sidewall having insulation property on at least one of said first conductive layers so that said sub-sidewall contacts a whole side surface of at least one of said main sidewalls opposite to said gate electrode;
doping impurities of the second conductivity type into exposed regions of said first conductive layers exposed through a mask using said gate electrode, said main sidewalls and said sub-sidewall so as to form heavily-doped impurity regions of said second conductivity type in which the density of said impurities is higher than said first conductive layers.
2 . The manufacturing method according to claim 1 , wherein said forming step of said main sidewalls includes the steps of:
forming a main-sidewall-forming film composed of a conductive material on said semiconductor substrate;
forming a first-sidewall-forming film on said main-sidewall-forming film;
etching said first-sidewall-forming film to thereby form first sidewalls on said side surfaces of said gate electrode; and
etching said main-sidewall-forming film and said first sidewalls to thereby form said main sidewalls on said side surfaces of said gate electrode.
3 . The manufacturing method according to claim 2 , wherein said main-sidewall-forming film is composed of polysilicon.
4 . The manufacturing method according to claim 2 , wherein said first-sidewall-forming film is formed of an oxide film.
5 . The manufacturing method according to claim 2 , wherein an etch-back technology is used in said etching step of said first-sidewall-forming film and in said etching step of said main-sidewall-forming film.
6 . The manufacturing method according to claim 1 , wherein said forming step of said sub-sidewall includes the steps of:
forming a sub-sidewall-forming film on said semiconductor substrate, said gate electrode and said main sidewalls; and
etching said sub-sidewall-forming film to thereby form said sub-sidewall on said side surface of said main sidewall.
7 . The manufacturing method according to claim 6 , wherein said sub-sidewall-forming film is formed of an oxide film.
8 . The manufacturing method according to claim 6 , wherein an etch-back technology is used in said etching step of said sub-sidewall-forming film.