IP Library Granted Patent US 7,718,449
Granted Patent B2
US 7,718,449 · App. 11/588,551 · Granted May 18, 2010

Wafer level package for very small footprint and low profile white LED devices

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Quick Facts
Patent No.
US 7,718,449
App. No.
11/588,551
Granted
May 18, 2010
Kind
B2
Abstract

A surface mount LED package having a tight footprint and small vertical image size is fabricated by a method comprising: forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing; forming electrical vias in a sub mount, the electrical vias passing from a front side of the sub-mount to a back-side of the sub-mount; flip chip bonding the light emitting diode chips on the front-side of the sub mount such that each light emitting diode chip electrically contacts selected electrical vias; thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

Claims (35)

1. A method for fabricating a light emitting diode package, the method comprising:

forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing;

forming electrical vias in a sub mount, the electrical vias passing from a front-side of the sub-mount to a back-side of the sub-mount;

flip chip bonding the light emitting diode chips on the front-side of the sub-mount such that each light emitting diode chip electrically contacts selected electrical vias;

thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and

after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

2. The method as set forth in claim 1 , further comprising:

after the disposing of the phosphor, separating the submount to form surface mount light emitting diode packages.

3. The method as set forth in claim 1 , further comprising:

disposing an underfill material between the front-side of the sub-mount and the light emitting diode chips.

4. The method as set forth in claim 3 , wherein the underfill material is disposed before flip-chip bonding.

5. The method as set forth in claim 3 , wherein the underfill material is disposed after the flip-chip bonding.

6. A method for fabricating a light emitting diode package, the method comprising:

forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing;

forming electrical vias in a sub-mount, the electrical vias passing from a front-side of the sub-mount to a back-side of the sub-mount;

flip chip bonding the light emitting diode chips on the front-side of the sub-mount such that each light emitting diode chip electrically contacts selected electrical vias;

removing the substrates of the flip-chip bonded light emitting diode chips; and

after the removing of the substrates, disposing a phosphor over the flip chip bonded light emitting diode chips.

7. The method as set forth in claim 6 , wherein the removing comprises removing the substrate by an optical lift-off process.

8. The method as set forth in claim 6 , wherein the removing comprises removing the substrate by a laser lift-off process.

9. The method as set forth in any one of claims 8 , wherein the light emitting diode chips are group III nitride-based light emitting diode chips.

10. The method as set forth in claim 9 , wherein the light emitting diode chips emit UV light and the disposing of a phosphor comprises disposing a phosphor that produces substantially white converted light.

11. The method as set forth in claim 9 , wherein the light emitting diode chips emit violet or blue light and the disposing of a phosphor comprises disposing a phosphor that produces substantially yellowish converted light that blends with the violet or blue light to output substantially white light.

12. The method as set forth in claim 1 , wherein the disposing of a phosphor comprises disposing a phosphor over substantially the entire frontside of the submount including the light emitting diode chips.

13. The method as set forth in claim 1 , wherein the disposing of a phosphor comprises disposing a phosphor over the light emitting diode chips without substantial disposing onto exposed areas of the frontside of the submount.

14. The method as set forth in claim 13 , wherein the disposing of a phosphor comprises disposing the phosphor over each light emitting diode chip in an area including the light emitting diode chip that is less than 20 microns larger than the light emitting diode chip.

15. A method for fabricating a light emitting diode package, the method comprising:

forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing;

forming electrical vias in a sub-mount, the electrical vias passing from a front-side of the sub-mount to a back-side of the sub-mount;

flip chip bonding the light emitting diode chips on the front-side of the sub-mount such that each light emitting diode chip electrically contacts selected electrical vias;

thinning or removing the substrates of the flip-chip bonded light emitting diode chips wherein the light emitting diode chips after thinning or removal of the substrate have thicknesses of less than 5 microns; and

after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

16. The method as set forth in claim 1 , wherein the disposing a phosphor comprises:

selectively deposited the phosphor in areas each encompassing and slightly larger than one of the light emitting diode chips.

17. The method as set forth in claim 16 , wherein the areas of selective phosphor deposition each extend less than 20 microns larger than the light emitting diode chip.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER PREVIOUSLY RECORDED AT REEL: 059034 FRAME: 0469. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jan 25, 2024
From: HUBBELL LIGHTING, INC.; LITECONTROL CORPORATION; CURRENT LIGHTING SOLUTIONS, LLC; DAINTREE NETWORKS INC.; FORUM, INC.
To: ATLANTIC PARK STRATEGIC CAPITAL FUND, L.P., AS COLLATERAL AGENT
Reel/Frame 066372/0590 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 10841994 TO PATENT NUMBER 11570872 PREVIOUSLY RECORDED ON REEL 058982 FRAME 0844. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Jan 19, 2024
From: HUBBELL LIGHTING, INC.; LITECONTROL CORPORATION; CURRENT LIGHTING SOLUTIONS, LLC; DAINTREE NETWORKS INC.; FORUM, INC.
To: ALLY BANK, AS COLLATERAL AGENT
Reel/Frame 066355/0455 →
SECURITY INTEREST Recorded Feb 11, 2022
From: HUBBELL LIGHTING, INC.; LITECONTROL CORPORATION; CURRENT LIGHTING SOLUTIONS, LLC; DAINTREE NETWORKS INC.; FORUM, INC.
To: ATLANTIC PARK STRATEGIC CAPITAL FUND, L.P., AS COLLATERAL AGENT
Reel/Frame 059034/0469 →
SECURITY AGREEMENT Recorded Feb 2, 2022
From: HUBBELL LIGHTING, INC.; LITECONTROL CORPORATION; CURRENT LIGHTING SOLUTIONS, LLC; DAINTREE NEETWORKS INC.; FORUM, INC.
To: ALLY BANK, AS COLLATERAL AGENT
Reel/Frame 058982/0844 →
CHANGE OF NAME Recorded Apr 9, 2019
From: GELCORE, LLC
To: LUMINATION, LLC
Reel/Frame 048830/0474 →
CHANGE OF NAME Recorded Apr 9, 2019
From: LUMINATION, LLC
To: GE LIGHTING SOLUTIONS, LLC
Reel/Frame 048832/0057 →
CHANGE OF NAME Recorded Apr 9, 2019
From: GE LIGHTING SOLUTIONS, LLC
To: CURRENT LIGHTING SOLUTIONS, LLC
Reel/Frame 048840/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2007
From: GAO, XIANG
To: LUMINATION, LLC
Reel/Frame 019268/0119 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2006
From: SACKRISION, MICHAEL
To: GELCORE LLC
Reel/Frame 018473/0878 →