IP Library Granted Patent US 7,671,404
Granted Patent B2
US 7,671,404 · App. 11/589,095 · Granted Mar 2, 2010

Fabrication method and structure of semiconductor non-volatile memory device

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Quick Facts
Patent No.
US 7,671,404
App. No.
11/589,095
Granted
Mar 2, 2010
Kind
B2
Abstract

A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Claims (31)

1. A non-volatile semiconductor memory device, comprising:

a semiconductor substrate;

first and second semiconductor regions formed in the semiconductor substrate;

a first region between the first semiconductor region and the second semiconductor region;

a charge accumulation region formed above the first region via a first insulator; and

wherein the charge density of an impurity on the side close to the second semiconductor region in the first region is higher than that on the side close to the first semiconductor region in the first region,

wherein the charge accumulation region is erased by injecting holes, and

wherein the holes are injected, from a part in the first region on the side closer to the second semiconductor region than the first semiconductor region, to the charge accumulation region,

wherein the first region comprises a second region located on the side close to the first semiconductor region and a third region located on the side close to the second semiconductor region,

wherein the charge accumulation region is formed above the third region and a first electrode is formed above the second region via an insulator, and

wherein the charge density of an impurity in the second region is higher than that in the third region.

2. The non-volatile semiconductor memory device according to claim 1 ,

wherein the charge accumulation region is programmed by injecting electrons.

3. The non-volatile semiconductor memory device according to claim 2 ,

wherein the electrons are injected, from a part in the first region on the side closer to the first semiconductor region than the second semiconductor region, to the charge accumulation region.

4. The non-volatile semiconductor memory device according to claim 1 ,

wherein the charge accumulation region is programmed by injecting electrons,

wherein the holes are injected, from a position on the side closer to the second semiconductor region in the third region than the first semiconductor region in the third region, to the charge accumulation region, and

wherein the electrons are injected, from a position on the side closer to the first semiconductor region in the third region than the second semiconductor region in the third region, to the charge accumulation region.

5. The non-volatile semiconductor memory device according to claim 4 ,

wherein the charge accumulation region is a nitridation film.

6. The non-volatile semiconductor memory device according to claim 4 ,

wherein the charge accumulation region is at a nitride film layer contained in a multi-layered insulation film.

7. The non-volatile semiconductor memory device according to claim 6 ,

wherein the multi-layered insulation layer is an Oxide Nitride Oxide (ONO) laminated film.

8. The non-volatile semiconductor memory device according to claim 1 ,

wherein the charge accumulation region is a nitridation film.

9. The non-volatile semiconductor memory device according to claim 8 ,

wherein the charge accumulation region is at a nitride film layer contained in a multi-layered insulation film.

10. The non-volatile semiconductor memory device according to claim 9 ,

wherein the multi-layered insulation layer is an Oxide Nitride Oxide (ONO) laminated film.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER AND CHANGE OF NAME Recorded Sep 9, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024964/0180 →