Power supply generating circuit, display apparatus, and portable terminal device
View Patent ↗A power supply generating circuit, a display apparatus incorporating the same, and a portable terminal device using the display apparatus as an output display unit are provided. In a DC-DC converter having a charge pump circuit ( 31 ), a voltage dividing circuit ( 32 ), and a regulation circuit ( 33 ), p-channel MOS transistors (Qp 21, Qp 22, Qp 31 ) are turned on/off based on an enable pulse enb to make the voltage dividing circuit ( 32 ) and a comparator ( 41 ) active only for a period of regulation time and inactive otherwise. This can cause a current to flow in voltage-divider resistors (R 1, R 2 ) and the comparator ( 41 ) only for a certain period of time required for the regulation operation, thus reducing the power consumption loss caused by a constant current flow in the voltage-divider resistors (R 1, R 2 ) and the comparator ( 41 ).
1. A power supply generating circuit comprising:
charge pump means for repeating charging in synchronization with a clock pulse;
voltage dividing means for dividing an output voltage of the charge pump means;
regulator means, having a comparator for comparing the divided voltage obtained from the voltage dividing means with a reference voltage, for controlling the supply of the clock pulse to the charge pump means based on the comparison result of the comparator; and
control means for making at least one of the voltage dividing means and the comparator active only for a certain period of time;
wherein the control means includes switching means connected between a voltage-divider point of the voltage dividing circuit and an input terminal of the comparator, and further wherein a clock state is combined with an output from the comparator as an input to the charge pump means in order to control its operation.
2. A power supply generating circuit according to claim 1 , wherein the regulation means includes holding means for holding the comparison result of the comparator.
3. A power supply generating circuit according to claim 2 , wherein the regulation means applies a logical AND of the clock which transitions at a time other than a sampling time of the holding means and a hold output of the holding means to the charge pump means.
4. A power supply generating circuit according to claim 2 , wherein the holding means comprises a sample-and-hold circuit or a latch circuit for sampling the comparison result of the comparator for a period for which at least one of the voltage dividing means and the comparator is active and for holding or latching it for a period other than that period, and
the comparator has an offset cancellation function and detects an offset for a certain period of time during the hold or latch period of the sample-and-hold circuit or latch circuit.
5. A power supply generating circuit comprising:
charge pump means for repeating charging in synchronization with a clock pulse;
voltage dividing means for dividing an output voltage of the charge pump means;
regulator means, having a comparator for comparing the divided voltage obtained from the voltage dividing means with a reference voltage, for controlling the supply of the clock pulse to the charge pump means based on the comparison result of the comparator; and
control means for electrically isolating the voltage dividing means from first and second voltages and further wherein a clock state is combined with an output from the comparator as an input to the charge pump means in order to control its operation.
6. A power supply generating circuit comprising:
charge pump means for repeating charging in synchronization with a clock pulse;
voltage dividing means for dividing an output voltage of the charge pump means;
regulator means, having a comparator for comparing the divided voltage obtained from the voltage dividing means with a reference voltage, for controlling the supply of the clock pulse to the charge pump means based on the comparison result of the comparator; and
control means for electrically isolating the voltage dividing means from first and second voltages and disconnecting the voltage dividing means from the comparator and further wherein a clock state is combined with an output from the comparator as an input to the charge pump means in order to control its operation.