Phase lock loop control error selection system and method
In one embodiment, a cross zero best error selection system includes an error input interface, a most significant bit summation component and a multiplexer. The error input interface in coupled to a most significant bit summation component which in turn is coupled to a multiplexer. The error input interface receives a plurality of future error values. The most significant bit summation component sums most significant bits of said future error values. The multiplexer for selects error value based upon said summation of said most significant bits.
1. A cross zero best error selection system comprising:
an error input interface for receiving a plurality of future error values;
a most significant bit summation component for summing most significant bits of said future error values; and
a multiplexer for selecting error value based upon said summation of said most significant bits.
2. A cross zero best error selection system of claim 1 wherein said summation of said most significant bits corresponds to an identification of said selected error value.
3. A cross zero best error selection system of claim 1 wherein said summation of said most significant bits is an index value associated with said selected error value.
4. A cross zero best error selection system of claim 3 wherein said most significant bit summation component is an adder.
5. A cross zero best error selection method comprising:
receiving a plurality of error values;
summing the most significant bits of said error values;
selecting one of said error values based upon results of said summing; and
forwarding said results of said summing as an identification of said selected one of said error values.
6. A cross zero best error selection method of claim 5 , further comprising forwarding said results of said selecting as an error feedback.
7. A cross zero best error selection method of claim 5 wherein said selecting includes multiplexing said errors in accordance with said summing of said error values.
8. A cross zero best error selection method of claim 5 wherein said results of summing said most significant bits is equal to an index of a cross zero point.
9. A cross zero best error selection method of claim 8 further comprising:
sorting errors in a monotonic order; and
storing said errors in said monotonic order, wherein said cross zero point is an index corresponding to a point in said monotonic order of errors.
10. A cross zero best error selection method of claim 5 further comprising:
receiving a modulation value;
mixing the modulation value with an initial error signal to produce a modulated error value;
merging the modulated error signal with one or more compensation vectors to produce a plurality of error values; and
picking a feedback divider value based upon said selected error value.
11. A cross zero best error selection method of claim 10 wherein a modulation signal pattern amplitude is determined based upon the resolution of vectors, spread spectrum percentage and an average PLL feedback divider value.
12. A frequency synthesizer comprising:
a phase lock loop component for creating a spread spectrum frequency signal;
a phase lock loop controller for controlling the phase lock loop component; and
a control pattern generation component for generating a spread spectrum control pattern comprising a sequence of values utilized by the phase lock loop controller to control the phase lock loop component, wherein said spread spectrum control pattern generated by said control pattern generation component is based upon summing the most significant bits of future error values and a result of said summing is an index to a selected position in monotonically ordered future error values, and wherein said control pattern generation component comprises:
an input modulation signal mixer for producing a modulated error signal,
an error combination component for producing a plurality of error signals based upon the modulated error signal,
a cross zero best error selection component for selectin one of the plurality of error signals and an identification of the one of the plurality of error signals, and
a control value selection component for selecting a divider value based upon the one of the plurality of error signals.
13. A frequency synthesizer of claim 12 wherein a modulation signal has a non-linear curve pattern.
14. A frequency synthesizer of claim 12 wherein a divider value is utilized to generate a fractional-N modulated frequency.
15. A frequency synthesizer of claim 12 wherein a divider value is utilized to generate a spread spectrum modulated frequency.
16. A frequency synthesizer of claim 12 wherein the control pattern generation component generates fractional-N control pattern.
17. A frequency synthesizer of claim 12 wherein the control pattern generation component utilizes vectors to represent a relationship between an average feedback.