Nanoscale electronic latch
View Patent ↗In one embodiment of the present invention, a nanoscale latch is implemented by interconnecting an enable line, two control lines, and a pull-down line, when needed, to a signal line carrying encoded binary values to be latched and subsequently output. The enable line is interconnected with the signal line through a field-effect-transistor-like nanoscale junction. Both control lines are interconnected with the signal line through asymmetric-switch nanoscale junctions of like polarities. The pull-down line, when needed, is interconnected with the signal line through a resistive nanoscale junction. Inputting a sequence of signals to the enable and control lines allows a value input from the signal line to be stored and subsequently output to the signal line. In various additional embodiments, an array of nanoscale latches can be implemented by overlaying enable and control lines, and a pull-down line when needed, over a set of parallel nanowires.
1. An electronic latch comprising:
a signal line on which a binary value is input for latching, and on which the latched binary value may be subsequently output;
an enable signal line interconnected with the signal line by a FET-like junction that controls input of a binary value on the signal line to the electronic latch;
a control-A signal line interconnected with the signal line by a first asymmetric-switch junction having a polarity; and
a control-B signal line interconnected with the signal line by a second asymmetric-switch junction having the same polarity as the first asymmetric-switch function.
2. The electronic latch of claim 1 further including, when the signal line is not grounded through a resistive connection:
a pull-down signal line connected with the signal line by a resistive junction and connected to ground.
3. The electronic latch of claim 2 wherein the signal line is a nanowire and the FET-like junction, asymmetric-switch junctions, and resistive junction are nanoscale junctions.
4. The electronic latch of claim 2 wherein the enable, control A, control B, and pull-down lines are each one of:
a nanowire;
a sub-micron-scale signal line; and
a microscale signal line.
5. An array of electronic latches of claim 1 , each electronic latch of the array of electronic latches having a different signal line, and all electronic latches of the array of electronic latches sharing common enable and control signal lines.
6. A two-dimensional array of electronic latches of claim 1 , each electronic latch of a row of the two-dimensional array of electronic latches sharing a common signal line, and each electronic latch of a column of the two-dimensional array of electronic latches the array of electronic latches sharing common enable and control signal lines.
7. The electronic latch of claim 1 wherein an asymmetric-switch junction can be opened, by applying a positive voltage across the asymmetric-switch junction, and can be closed, by applying a negative voltage across the asymmetric-switch junction, the state of the asymmetric switch stable in a range of applied voltages between the closing voltage and the opening voltage.
8. The electronic latch of claim 1 wherein an encoded binary value input to the electronic latch on the signal line is latched by:
latching the binary value in the first asymmetric-switch junction; and
latching the binary value in the second asymmetric-switch junction.
9. The electronic latch of claim 1 wherein latching the binary value in the first asymmetric-switch junction further comprises:
opening the FET-like junction;
opening the second asymmetrical-switch junction;
closing the first asymmetrical-switch junction;
closing the FET-like junction to input a binary value to the latch; and
asserting a positive voltage on the control-A signal line so that the asymmetric-switch junction remains closed, when the binary value is high, and is opened, when the binary value is low.
10. The electronic latch of claim 1 wherein latching the binary value in the second asymmetric-switch junction further comprises:
opening the FET-like junction;
asserting a negative voltage on the control-A signal line; and
asserting a negative voltage on the control-B signal line so that the second asymmetrical-switch junction remains open, when the binary value is high, and closes, when the binary value is low.
11. The electronic latch of claim 1 wherein a latched binary value is output to the electronic latch on the signal line by:
while the FET-like junction is open,
asserting a positive voltage on the control-A signal line and asserting a negative voltage on the control-B signal line.
12. The electronic switch of claim 1 wherein an inverted binary value corresponding to a latched binary value is output to the electronic latch on the signal line by:
while the FET-like junction is open,
asserting a negative voltage on the control-A signal line and asserting a positive voltage on the control-B signal line.
13. A method for implementing an electronic latch comprising:
providing a signal line on which a binary value is input for latching, and on which the latched binary value may be subsequently output;
interconnecting an enable signal line with the signal line through a FET-like junction that controls input of a binary value on the signal line to the electronic latch;
interconnecting a control-A signal line with the signal line through a first asymmetric-switch junction having a polarity; and
interconnecting a control-B signal line with the signal line through a second asymmetric-switch junction having the same polarity as the first asymmetric-switch function.
14. The method of claim 13 further including, when the signal line is not grounded through a resistive connection:
interconnecting a pull-down signal line with the signal line through a resistive junction and connected to ground.
15. The method of claim 14 wherein the signal line is a nanowire and the FET-like junction, asymmetric-switch junctions, and resistive junction are nanoscale junctions.
16. The method of claim 13 wherein an encoded binary value input to the electronic latch on the signal line is latched by:
latching the binary value in the first asymmetric-switch junction; and
latching the binary value in the second asymmetric-switch junction.
17. The method of claim 16 wherein latching the binary value in the first asymmetric-switch junction further comprises:
opening the FET-like junction;
opening the second asymmetrical-switch junction;
closing the first asymmetrical-switch junction;
closing the FET-like junction to input a binary value to the latch; and
asserting a positive voltage on the control-A signal line so that the asymmetric-switch junction remains closed, when the binary value is high, and is opened, when the binary value is low.
18. The method of claim 16 wherein latching the binary value in the second asymmetric-switch junction further comprises:
opening the FET-like junction;
asserting a negative voltage on the control-A signal line; and
asserting a negative voltage on the control-B signal line so that the second asymmetrical-switch junction remains open, when the binary value is high, and closes, when the binary value is low.
19. The method of claim 13 wherein a latched binary value is output to the electronic latch on the signal line by:
while the FET-like junction is open,
asserting a positive voltage on the control-A signal line and asserting a negative voltage on the control-B signal line.
20. The method of claim 13 wherein an inverted binary value corresponding to a latched binary value is output to the electronic latch on the signal line by:
while the FET-like junction is open,
asserting a negative voltage on the control-A signal line and asserting a positive voltage on the control-B signal line.