System, method, and computer program product for shared memory queue
In summary, one aspect of the present invention is directed to a method for a shared memory queue to support communicating between computer processes, such as an enqueuing process and a dequeuing process. A buffer may be allocated including at least one element having a data field and a reserve field, a head pointer and a tail pointer. The enqueuing process may enqueue a communication into the buffer using mutual exclusive access to the element identified by the head pointer. The dequeuing process may dequeue a communication from the buffer using mutual exclusive access to the element identified by the tail pointer. Mutual exclusive access to said head pointer and tail pointer is not required. A system and computer program for a shared memory queue are also disclosed.
1 . A network processor system capable of supporting interrupt scheduling, said system including:
a plurality of processors with each processor capable of executing at least one process;
a first process of said at least one process, coupled with a processor of said plurality of processors, said first process executing a first program including at least one first instruction capable of receiving a first packet and enqueuing a first communication;
a second process of said at least one process, coupled with a processor of said plurality of processors, said second process executing a second program including at least one second instruction capable of identifying a destination address of said packet, said second program coupled with a first allocated buffer interface to said first program, said second program is capable of dequeuing the first communication enqueued by said first program, and capable of enqueuing a second communication; and
a third process of said at least one process, coupled with a processor of said plurality of processors, said third process executing a third program including at least one third instruction capable of sending a second packet to said destination address in response to receiving said first packet, said third program coupled with a second allocated buffer interface to said second program, said third program is capable of dequeuing the second communication enqueued by said second program.
2 . The network processor system of claim 1 , wherein said first allocated buffer interface is coupled with a first allocated buffer having:
at least one element for enqueuing and dequeuing said first communication;
a head pointer coupled with a head element selected from said at least one element; and
a tail pointer coupled with a tail element selected from said at least one element; and
said enqueuing and said dequeuing includes mutual exclusive access to said head element and said tail element respectively, without mutual exclusive access to said head pointer or said tail pointer.
3 . A method for interrupt scheduling, said method comprising:
executing a first process that executes a first program including at least one first instruction capable of receiving a first packet and enqueuing a first communication;
executing a second process that executes a second program including at least one second instruction capable of identifying a destination address of said packet, said second program coupled with a first allocated buffer interface to said first program, said second program being capable of dequeuing the first communication enqueued by said first program, and capable of enqueuing a second communication; and
executing a third process that executes a third program including at least one third instruction capable of sending a second packet to said destination address in response to receiving said first packet, said third program coupled with a second allocated buffer interface to said second program, said third program is capable of dequeuing the second communication enqueued by said second program.
4 . The method of claim 3 , further comprising coupling said first allocated buffer interface with a first allocated buffer having:
at least one element for enqueuing and dequeuing said first communication;
a head pointer coupled with a head element selected from said at least one element; and
a tail pointer coupled with a tail element selected from said at least one element; and
said enqueuing and said dequeuing includes mutual exclusive access to said head element and said tail element respectively, without mutual exclusive access to said head pointer or said tail pointer.
5 . The method of claim 3 , further comprising: providing a plurality of processors with each processor capable of executing at least one process, and executing the first process, the second process, and the third process in this plurality of processors.
6 . A network processor supporting interrupt scheduling, said network processor comprising:
a plurality of processors each for executing at least one process;
a first process executing in a first of said plurality of processors, said first process executing at least one first instruction for receiving a first packet and enqueuing a first communication;
a second process executing in a second of said plurality of processors, said second process executing at least one second instruction for identifying a destination address of said first packet, said second program using a first allocated buffer interface to said first process, said second process operative to dequeue the first communication enqueued by said first process and to enqueue a second communication; and
a third process executing in a third of said plurality of processors, said third process executing at least one third instruction for sending a second packet to said destination address in response to receiving said first packet, said third process using a second allocated buffer interface to said second process and operative to dequeue the second communication enqueued by said second program.