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App. No. 11/590,803 · Confirmation No. 6423

Memory circuit

Inventor: Yuuichirou Ikeda
Abandoned -- Failure to Respond to an Office Action View Publication ↗
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 Code Description Pages PDF
2009-10-28 ABN Abandonment 2 View
2009-03-27 CTNF Non-Final Rejection 11 View
2009-03-27 892 List of references cited by examiner 1 View
2009-03-27 BIB Bibliographic Data Sheet 1 View
2009-03-27 FWCLM Index of Claims 1 View
2009-03-27 SRFW Search information including classification, databases and other search related notes 1 View
2009-03-27 SRNT Examiner's search strategy and results 12 View
2009-03-27 1449 List of References cited by applicant and considered by examiner 1 View
2007-05-10 NTC.PUB Notice of Publication 1 View
2006-11-16 APP.FILE.REC Filing Receipt 3 View
2006-11-01 TRNA Transmittal of New Application 2 View
2006-11-01 SPEC Specification 19 View
2006-11-01 CLM Claims 5 View
2006-11-01 ABST Abstract 1 View
2006-11-01 DRW Drawings-only black and white line drawings 4 View
2006-11-01 OATH Oath or Declaration filed 2 View
2006-11-01 WFEE Fee Worksheet (SB06) 1 View
2006-11-01 WFEE Fee Worksheet (SB06) 1 View
2006-11-01 IDS Information Disclosure Statement (IDS) Form (SB08) 3 View
2006-11-01 FRPR Certified Copy of Foreign Priority Application 21 View
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Quick Facts
App. No.
11/590,803
Filed
2006-11-01
Pub. No.
US20070103954A1
Examiner
YANG, HAN
Art Unit
2824