IP Library Granted Patent US 7,583,347
Granted Patent B2
US 7,583,347 · App. 11/590,810 · Granted Sep 1, 2009

Liquid crystal display having electrodes constituted by a transparent electric conductor

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Quick Facts
Patent No.
US 7,583,347
App. No.
11/590,810
Granted
Sep 1, 2009
Kind
B2
Abstract

A liquid crystal display including: a liquid crystal panel including an array substrate having an upper surface on which a common electrode and a pixel electrode are formed, an opposing substrate disposed so as to be opposite to the upper surface and a liquid crystal layer disposed between the array substrate and the opposing substrate, and a reflecting face. The liquid crystal display is further characterized in that at least one electrode of the common electrode and the pixel electrode is constituted by an electrode portion and a wiring portion, the electrode portion is at least partially constituted by a transparent electric conductor, the electrode portion is formed in a layer separated by an insulating layer from a layer in which the scanning signal line is formed, and the wiring portion is formed in the layer in which the scanning signal line is formed.

Claims (12)

1. A liquid crystal display comprising:

a liquid crystal panel including an array substrate having an upper surface on which a common electrode, a pixel electrode, a scanning signal line, a video signal line, and a semiconductor switching device are formed, an opposing substrate disposed so as to be opposite to the upper surface of the array substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate, and

a reflecting face formed below the liquid crystal panel, wherein a light reflected on the reflecting face is transmitted through the liquid crystal panel, and wherein

at least one electrode of the common electrode and the pixel electrode is constituted by an electrode portion and a wiring portion,

the electrode portion is at least partially constituted by a transparent electric conductor,

the electrode portion is formed in a layer separated by an insulating layer from a layer in which the scanning signal line is formed, and

the wiring portion is formed in the layer in which the scanning signal line is formed.

2. The liquid crystal display according to claim 1 , wherein the common electrode and the pixel electrode are both constituted by a wiring portion and a comb-shaped electrode portion, and a width of the electrode portion at least partially constituted by a transparent electric conductor is different from a width of a part of the electrode portion which is not constituted by a transparent electric conductor.

3. The liquid crystal display according to claim 2 , wherein the width of the electrode portion partially constituted by a transparent electric conductor is larger than the width of the part of the electrode portion which is not constituted by a transparent electric conductor.

4. The liquid crystal display according to claim 2 , wherein a width of each electrode portion of the common electrode and the pixel electrode is 1 μm or more and 10 μm or less.

5. The liquid crystal display according to claim 1 , wherein the common electrode and the pixel electrode are both constituted by a wiring portion and a comb-shaped electrode portion, and widths of both of the electrode portions of the common electrode and the pixel electrode are structured for liquid crystal molecules disposed above the electrode portion partially constituted by a transparent electric conductor to be modulated by an electric field generated between the electrode portion of the common electrode and the electrode portion of the pixel electrode.

6. The liquid crystal display according to claim 5 , wherein at least one of the width of each electrode portion of the common electrode and the pixel electrode, and a spacing between the electrode portions of the common electrode and the pixel electrode is substantially equal to or smaller than a spacing between the array substrate and the opposing substrate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2021
From: PARKSIDE IP LLC
To: BISHOP DISPLAY TECH LLC
Reel/Frame 055513/0854 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: GODO KAISHA IP BRIDGE 1
To: PARKSIDE IP LLC
Reel/Frame 053196/0829 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2014
From: PANASONIC CORPORATION (FORMERLY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.)
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032152/0514 →