Method and apparatus for detecting degradation in an integrated circuit chip
A system that detects degradation in an integrated circuit chip. During operation, the system monitors a pair of pins on the integrated circuit chip and in doing so, generates a time series of parameters for the pins. The system then determines whether the time series of parameters indicates that the integrated circuit chip has degraded. If so, the system generates a signal indicating that the integrated circuit chip has degraded.
1. A method for detecting degradation in an integrated circuit chip, comprising:
monitoring a pair of pins on the integrated circuit chip to generate a time series of parameters for the pins;
determining whether the time series of parameters indicates that the integrated circuit chip has degraded; and
if so, generating a signal indicating that the integrated circuit chip has degraded.
2. The method of claim 1 , wherein determining whether the time series of parameters indicates that the integrated circuit chip has degraded involves:
calculating pair-wise differences between the parameters obtained from the pair of pins to produce a difference function; and
determining whether the difference function indicates that the integrated circuit chip is has degraded.
3. The method of claim 2 , determining whether the difference function indicates that the integrated circuit chip is has degraded involves using a sequential probability ratio test (SPRT) to determine whether the difference function has deviated from a nominally stationary noisy process.
4. The method of claim 3 , wherein the SPRT test can include one of more of:
a positive-mean test, which tests whether the mean of a time-series for the inferential variable is above a reference level;
a negative-mean test, which tests whether the mean of the time-series for the inferential variable is below a reference level;
a nominal-variance test, which tests whether the variance of the time-series for the inferential variable is proportional to a scale factor;
a inverse-variance test, which tests whether the variance of the time-series for the inferential variable is proportional to the inverse of the scale factor;
a positive first-difference test, which tests whether the time-series for the inferential variable is increasing;
a negative first-difference test, which tests whether the time-series for the inferential variable is decreasing;
a positive first-difference variance test, which tests whether the first difference of the variance of the time-series is increasing; and
a negative first-difference variance test, which tests whether the first difference of the variance of the time-series is decreasing.
5. The method of claim 1 , wherein the pair of pins are adjacent pins on the integrated circuit chip.
6. The method of claim 5 , wherein all pairs of adjacent pins on the integrated circuit chip are monitored.
7. The method of claim 1 , wherein monitoring the pair of pins involves monitoring voltages on the pair of pins.
8. The method of claim 1 , wherein monitoring the pair of pins involves monitoring an inter-lead impedance between the pair of pins.
9. The method of claim 1 , wherein determining whether the integrated circuit chip has degraded involves determining whether electromigration has occurred between leads associated with the pair of pins.
10. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for detecting degradation in an integrated circuit chip, wherein the method comprises:
monitoring a pair of pins on the integrated circuit chip to generate a time series of parameters for the pins;
determining whether the time series of parameters indicates that the integrated circuit chip has degraded; and
if so, generating a signal indicating that the integrated circuit chip has degraded.
11. The computer-readable storage medium of claim 10 , wherein determining whether the time series of parameters indicates that the integrated circuit chip has degraded involves:
calculating pair-wise differences between the parameters obtained from the pair of pins to produce a difference function; and
determining whether the difference function indicates that the integrated circuit chip is has degraded.
12. The computer-readable storage medium of claim 11 , determining whether the difference function indicates that the integrated circuit chip is has degraded involves using a sequential probability ratio test (SPRT) to determine whether the difference function has deviated from a nominally stationary noisy process.
13. The computer-readable storage medium of claim 12 , wherein the SPRT test can include one of more of:
a positive-mean test, which tests whether the mean of a time-series for the inferential variable is above a reference level;
a negative-mean test, which tests whether the mean of the time-series for the inferential variable is below a reference level;
a nominal-variance test, which tests whether the variance of the time-series for the inferential variable is proportional to a scale factor;
a inverse-variance test, which tests whether the variance of the time-series for the inferential variable is proportional to the inverse of the scale factor;
a positive first-difference test, which tests whether the time-series for the inferential variable is increasing;
a negative first-difference test, which tests whether the time-series for the inferential variable is decreasing;
a positive first-difference variance test, which tests whether the first difference of the variance of the time-series is increasing; and
a negative first-difference variance test, which tests whether the first difference of the variance of the time-series is decreasing.
14. The computer-readable storage medium of claim 10 , wherein the pair of pins are adjacent pins on the integrated circuit chip.
15. The computer-readable storage medium of claim 14 , wherein all pairs of adjacent pins on the integrated circuit chip are monitored.
16. The computer-readable storage medium of claim 10 , wherein monitoring the pair of pins involves monitoring voltages on the pair of pins.
17. The computer-readable storage medium of claim 10 , wherein monitoring the pair of pins involves monitoring an inter-lead impedance between the pair of pins.
18. The computer-readable storage medium of claim 10 , wherein determining whether the integrated circuit chip has degraded involves determining whether electromigration has occurred between leads associated with the pair of pins.
19. An apparatus that detects degradation in an integrated circuit chip, comprising a degradation-detection mechanism configured to:
monitor a pair of pins on the integrated circuit chip to generate a time series of parameters for the pins;
determine whether the time series of parameters indicates that the integrated circuit chip has degraded; and
if so, to generate a signal indicating that the integrated circuit chip has degraded.
20. The apparatus of claim 19 , wherein while determining whether the time series of parameters indicates that the integrated circuit chip has degraded, the degradation-detection mechanism is configured to:
calculate pair-wise differences between the parameters obtained from the pair of pins to produce a difference function; and to
determine whether the difference function indicates that the integrated circuit chip is has degraded.