Implementation of a DV video decoder with a VLIW processor and a variable length decoding unit
View Patent ↗A decoder for decoding a plurality of digital video data is described. In an embodiment, the decoder comprises a DV video decoder for decoding digital video data which is formatted according to the DV standard. The DV video decoder has a Very-Long Instruction Word (VLIW) processor and a variable length decoding unit. The VLIW processor includes a preparser unit for recovering a decoding order of the digital video data so that the variable length decoding unit can process the digital video data. The variable length decoding unit decodes a variable length coding format of the digital video data which has been preparsed by the VLIW processor. Furthermore, the VLIW processor includes a decompression unit for decompressing the digital video data which has been decoded by the variable length decoding unit. In an embodiment, the VLIW processor and the variable length decoding unit are formed on the same semiconductor device.
1. A method of processing digital video data comprising:
preparsing said digital video data to recover a decoding order of said digital video data operable to generate a contiguous digital video data; determining an end of data block associated with said decoding order; and decoding said contiguous digital video data in response to said end of block determination to produce decoded digital video data;
and wherein said determining a decoding order comprises: identifying blocks of said digital video data where coefficients of a variable block are stored as overflow data on more than one block; associating overflow data corresponding to said variable block; and aggregating coefficients of said variable block such that said contiguous digital video data is generated.
2. The method as described in claim 1 , further comprising: inserting an end of block indicator for blocks missing an end of block indicator.
3. An article of manufacture comprising a non-transitory computer readable storage medium comprising computer executable instructions operable on processors for performing a method of processing digital video data, said method comprising: preparsing said digital video data to recover a decoding order of said digital video data operable to generate a contiguous digital video data; determining an end of data block associated with said decoding order; and decoding said contiguous digital video data in response to said end of block determination to produce decoded digital video data;
and wherein said determining a decoding order comprises: identifying blocks of said digital video data where coefficients of a variable block are stored as overflow data on more than one block; associating overflow data corresponding to said variable block; and aggregating coefficients of said variable block such that said contiguous digital video data is generated.
4. The article of manufacture non-transitory computer readable storage medium as described in claim 3 , wherein said method further comprises: inserting an end of block indicator for blocks missing an end of block indicator.
5. An apparatus for processing digital video data, said apparatus comprising: a processor configured to determine a decoding order of said digital video data operable to generate a contiguous digital video data, and further configured to determine an end of data block associated with said decoding order; and
a decoding unit coupled to said processor, wherein said decoding unit is configured to decode said contiguous digital video data in response to said end of block determination
and wherein said processor is further configurable to identify blocks of said digital video data where coefficients of a variable block is stored as overflow data on more than one block, and wherein said processor is further configurable to associate overflow data corresponding to said variable block, and wherein said processor is further configurable to aggregate coefficients of said variable block such that said contiguous digital video data is generated.
6. The apparatus as described in claim 5 , wherein said processor is further configurable to insert an end of block indicator for blocks missing an end of block indicator.
7. An apparatus comprising: means for preparsing said digital video data to recover a decoding order of said digital video data operable to generate a contiguous digital video data; means for determining an end of data block associated with said decoding order; and means for decoding said contiguous digital video data in response to said end of block determination to produce decoded digital video data,
and wherein said determining a decoding order comprises: means for identifying blocks of said digital video data where coefficients of a variable block are stored as overflow data on more than one block; means for associating overflow data corresponding to said variable block; and means for aggregating coefficients of said variable block such that said contiguous digital video data is generated.
8. The apparatus method as described in claim 7 , further comprising: means for inserting an end of block indicator for blocks missing an end of block indicator.