Thin film transistor array substrate and manufacturing method of the same
View Patent ↗A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode formed and superimposed with the gate line; a semiconductor pattern formed in low part of the substrate; a transparent electrode pattern including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode covering the data pad; and a protection pattern and a gate insulation pattern stacked in a region other than the region where the transparent electrode pattern is formed.
1. A thin film transistor array substrate, comprising:
a gate pattern including:
a gate electrode of the thin film transistor;
a gate line to which the gate electrode is connected; and
a gate pad to which the gate line is connected;
a source/drain pattern including:
a source electrode and a drain electrode of the thin film transistor;
a data line connected to the source electrode;
a data pad connected to the data line;
a storage electrode formed and superimposed with the gate line;
a semiconductor pattern formed in a low region of the substrate corresponding to the source/drain pattern;
a transparent electrode including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode formed to cover the data pad; and
a protection pattern and a gate insulation pattern stacked in the remainder region except for the region where the transparent electrode pattern is formed.
2. The thin film transistor array substrate according to claim 1 , wherein the protection pattern partially exposes the drain electrode and the storage electrode and is connected to the pixel electrode.
3. A thin film transistor array substrate, comprising:
a gate electrode of the thin film transistor;
a gate line to which the gate electrode is connected; and
a gate pad to which the gate line is connected;
a source electrode and a drain electrode of the thin film transistor;
a data line connected to the source electrode;
a data pad connected to the data line;
a storage electrode formed and superimposed over the gate line;
a transparent electrode including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode formed to cover the data pad; and
a protection layer and a gate insulation layer stacked in a region of the substrate other than the region where the transparent electrode is formed.
4. The thin film transistor array substrate according to claim 3 , wherein the protection layer partially exposes the drain electrode and the storage electrode and is connected to the pixel electrode.