Liquid crystal display panel with dual-TFTs pixel units having different TFT channel width/length ratios
View Patent ↗An exemplary liquid crystal display ( 200 ) includes a plurality of gate lines ( 201 ), data lines ( 202 ), common lines ( 210 ), first pixel electrodes ( 204 ) and second pixel electrodes ( 214 ). Each of areas defined by one of the first pixel electrodes and an adjacent one of the second pixel electrodes is a pixel unit ( 208 ). Each pixel unit is driven by a first TFT ( 203 ) and a second TFT ( 213 ). The first thin film transistor and the second thin film transistor in each pixel unit are connected to a same one of the gate lines and a same one of the data lines, and to the first pixel electrode and the second pixel electrode respectively. A channel width/length ratio of the first thin film transistor is different from a channel width/length ratio of the second thin film transistor.
1. A liquid crystal display panel, comprising:
a plurality of gate lines;
a plurality of data lines intersecting with the gate lines;
a plurality of first pixel electrodes and a plurality of second pixel electrodes, wherein each of areas defined by one of the first pixel electrodes and an adjacent one of the second pixel electrodes is a pixel unit; and
a plurality of first thin film transistors and second thin film transistors, wherein each of the pixel units comprises one of the first thin film transistors and one of the second thin film transistors, the first thin film transistor and the second thin film transistor in each pixel unit are connected to a same one of the gate lines and a same one of the data lines, and to the first pixel electrode and the second pixel electrode respectively, and a channel width/length ratio of the first thin film transistor is different from a channel width/length ratio of the second thin film transistor.
2. The liquid crystal display panel as claimed in claim 1 , wherein gate electrodes of the first thin film transistor and the second thin film transistor are both connected to the same gate line.
3. The liquid crystal display panel as claimed in claim 1 , wherein source electrodes of the first thin film transistor and the second thin film transistor are both connected to the same data line.
4. The liquid crystal display panel as claimed in claim 1 , wherein the channel width/length ratio of the first thin film transistor is in the range from 1.5˜2.5 times larger than the channel width/length ratio of the second thin film transistor.
5. The liquid crystal display panel as claimed in claim 4 , wherein the channel width/length ratio of the first thin film transistor is approximately 2 times larger than the channel width/length ratio of the second thin film transistor.
6. The liquid crystal display panel as claimed in claim 1 , further comprising a common electrode, wherein a plurality of liquid crystal (LC) capacitors is formed between the common electrode and the first pixel electrodes and between the common electrode and the second pixel electrodes.
7. The liquid crystal display panel as claimed in claim 6 , further comprising a plurality of common lines, wherein in each pixel unit, the first pixel electrode and a corresponding one of the common lines forms a first storage capacitor, the second pixel electrode and another corresponding one of the common lines forms a second storage capacitor, the first storage capacitor is connected in parallel with the LC capacitor of the first pixel electrode, and the second storage capacitor is connected in parallel with the LC capacitor of the second pixel electrode.
8. A liquid crystal display panel, comprising:
a first transparent substrate, a second transparent substrate, and a liquid crystal layer interposed between the first transparent substrate and the second transparent substrate;
a plurality of gate lines and common lines provided at the first transparent substrate;
a plurality of data lines crossing the gate lines and common lines at the first transparent substrate; and
a plurality of pixel units each surrounded by two respective adjacent common lines and two respective adjacent data lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, a first thin film transistor associated with the first pixel electrode, and a second thin film transistor associated with the second pixel electrode, wherein the first thin film transistor and the second thin film transistor are respectively connected to a same gate line, a same data line, and the corresponding first pixel electrode or second pixel electrode, and a channel width/length ratio of each of the first thin film transistor and second thin film transistor are different from each other.
9. The liquid crystal display panel as claimed in claim 8 , wherein gate electrodes of the first thin film transistor and the second thin film transistor are both connected to the same gate line.
10. The liquid crystal display panel as claimed in claim 8 , wherein source electrodes of the first thin film transistor and the second thin film transistor are both connected to the same data line.
11. The liquid crystal display panel as claimed in claim 8 , wherein the channel width/length ratio of the first thin film transistor is in the range from 1.5˜2.5 times larger than the channel width/length ratio of the second thin film transistor.
12. The liquid crystal display panel as claimed in claim 11 , wherein the channel width/length ratio of the first thin film transistor is approximately 2 times larger than the channel width/length ratio of the second thin film transistor.
13. The liquid crystal display panel as claimed in claim 8 , further comprising a common electrode disposed at the second transparent substrate, wherein in each pixel unit, a first liquid crystal (LC) capacitor is formed between the common electrode and the first pixel electrode, and a second LC capacitor is formed between the common electrode and the second pixel electrode.
14. The liquid crystal display panel as claimed in claim 13 , further comprising a plurality of common lines, wherein in each pixel unit, the first pixel electrode and a corresponding one of the common lines forms a first storage capacitor, the second pixel electrode and another corresponding one of the common lines forms a second storage capacitor, the first storage capacitor is connected in parallel with the LC capacitor of the first pixel electrode, and the second storage capacitor is connected in parallel with the LC capacitor of the second pixel electrode.