Flash memory and method for manufacturing the same
View Patent ↗Provided are a flash memory and a method for manufacturing the same. The flash memory includes a semiconductor substrate having a device isolation region and an active region; a stacked gate on the semiconductor substrate; an insulation layer covering the semiconductor substrate and the stacked gate; a drain contact penetrating the insulation layer on one side of the stacked gate; and a source line penetrating the insulation layer on an opposite side of the stacked gate.
1. A method for manufacturing a flash memory, the method comprising:
forming a device isolation region and an active region on a semiconductor substrate;
forming a stacked gate on the active region by a process comprising forming a gate insulation layer on the semiconductor substrate, forming a floating gate on the gate insulation layer, forming a dielectric layer on the floating gate, and forming a control gate on the dielectric layer,
forming source and drain regions on opposite sides of the stacked gate;
forming salicide on a top surface of the stacked gate and on the drain regions; and
forming a drain contact on the salicide on the drain region, and a source line directly on the source regions, such that the source line is formed higher than the salicide.
2. The method according to claim 1 , wherein forming the salicide comprises:
forming a spacer on a sidewall of the stacked gate; and
depositing and heating a metal layer on the stacked gate, the spacer, and the semiconductor substrate.
3. The method according to claim 2 , wherein the metal layer comprises cobalt.
4. The method according to claim 2 , wherein the metal layer comprises titanium.
5. The method according to claim 1 , farther comprising, after forming the stacked gate, forming a barrier dielectric layer covering the semiconductor substrate and the stacked gate.
6. The method according to claim 5 , wherein the barrier dielectric layer comprises a nitride layer.
7. The method according to claim 1 , wherein forming the device isolation region comprises a STI (shallow trench isolation) process.
8. The method according to claim 1 , wherein forming the metal contact and the source line comprises:
forming an insulation layer covering the semiconductor substrate and the stacked gate;
etching the insulation layer to form a drain contact hole and a source line opening in the insulation layer; and
forming the drain contact and the source line alter the etching.
9. The method according to claim 1 , wherein the drain contact and the source line comprise tungsten.
10. The method according to claim 1 , wherein the drain contact and the source line are formed simultaneously by a CVD (chemical vapor deposition) process.
11. The method according to claim 8 , wherein the source line extends to a top surface of the insulation layer.
12. The method according to claim 1 , wherein the drain contact extends above the stacked gate.
13. The method according to claim 1 , wherein the device isolation region comprises a shallow trench isolation (STI) or a LOCOS (LOCal Oxidation of Silicon) field oxide structure.
14. The method according to claim 13 , wherein the device isolation region comprises the STI field oxide structure, and the source line is not in the trench of the STI field oxide structure.
15. The method according to claim 1 , wherein forming the drain contact and the source line comprises:
forming an insulation layer covering the semiconductor substrate and the stacked gate;
etching the insulation layer to form a drain contact hole and a source line opening in the insulation layer; and
forming the drain contact and the source line alter etching the insulation layer.
16. The method according to claim 14 , wherein the drain contact and the source line comprise tungsten.
17. The method according to claim 14 , wherein the drain contact and the source line are formed simultaneously by a CVD) (chemical vapor deposition) process.
18. The method according to claim 15 , wherein the source line extends to a top surface of the barrier dielectric layer.