SRAM circuit having a SONOS-based NAND device
The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.
1 . A SRAM circuit comprising:
a transistor having a source, gate and drain,
a bitline coupled to said source,
a wordline coupled to said gate, and
a resonant tunneling device coupled to said drain and a load.
2 . A SONOS-based NAND device comprising:
a top layer,
a resonant tunneling barrier layer, and
a small bandgap trapping layer sandwiched between said top layer and said resonant tunneling barrier layer.
3 . An integrated circuit comprising:
an SRAM circuit as claimed in claim 1 , and
a SONOS-based NAND device as claimed in claim 2.